OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity

tidy up. 

llvm-svn: 117166
This commit is contained in:
Jim Grosbach 2010-10-22 22:15:48 +00:00
parent 2c9ae05c67
commit b40a60fa2f
1 changed files with 13 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
llvm/test/MC/ARM/simple-encoding.ll
View File

@ -11,7 +11,6 @@ declare void @llvm.trap() nounwind
declare i32 @llvm.ctlz.i32(i32) declare i32 @llvm.ctlz.i32(i32)
define i32 @foo(i32 %a, i32 %b) { define i32 @foo(i32 %a, i32 %b) {
entry:
; CHECK: foo ; CHECK: foo
; CHECK: trap @ encoding: [0xf0,0x00,0xf0,0x07] ; CHECK: trap @ encoding: [0xf0,0x00,0xf0,0x07]
; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
@ -21,7 +20,6 @@ entry:
} }
define i32 @f2(i32 %a, i32 %b) { define i32 @f2(i32 %a, i32 %b) {
entry:
; CHECK: f2 ; CHECK: f2
; CHECK: add r0, r1, r0 @ encoding: [0x00,0x00,0x81,0xe0] ; CHECK: add r0, r1, r0 @ encoding: [0x00,0x00,0x81,0xe0]
; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
@ -31,7 +29,6 @@ entry:
define i32 @f3(i32 %a, i32 %b) { define i32 @f3(i32 %a, i32 %b) {
entry:
; CHECK: f3 ; CHECK: f3
; CHECK: add r0, r0, r1, lsl #3 @ encoding: [0x81,0x01,0x80,0xe0] ; CHECK: add r0, r0, r1, lsl #3 @ encoding: [0x81,0x01,0x80,0xe0]
; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
@ -41,7 +38,6 @@ entry:
} }
define i32 @f4(i32 %a, i32 %b) { define i32 @f4(i32 %a, i32 %b) {
entry:
; CHECK: f4 ; CHECK: f4
; CHECK: add r0, r0, #254, 28 @ encoding: [0xfe,0x0e,0x80,0xe2] ; CHECK: add r0, r0, #254, 28 @ encoding: [0xfe,0x0e,0x80,0xe2]
; CHECK: @ 4064 ; CHECK: @ 4064
@ -51,7 +47,6 @@ entry:
} }
define i32 @f5(i32 %a, i32 %b, i32 %c) { define i32 @f5(i32 %a, i32 %b, i32 %c) {
entry:
; CHECK: f5 ; CHECK: f5
; CHECK: cmp r0, r1 @ encoding: [0x01,0x00,0x50,0xe1] ; CHECK: cmp r0, r1 @ encoding: [0x01,0x00,0x50,0xe1]
; CHECK: mov r0, r2 @ encoding: [0x02,0x00,0xa0,0xe1] ; CHECK: mov r0, r2 @ encoding: [0x02,0x00,0xa0,0xe1]
@ -62,7 +57,6 @@ entry:
} }
define i64 @f6(i64 %a, i64 %b, i64 %c) { define i64 @f6(i64 %a, i64 %b, i64 %c) {
entry:
; CHECK: f6 ; CHECK: f6
; CHECK: adds r0, r2, r0 @ encoding: [0x00,0x00,0x92,0xe0] ; CHECK: adds r0, r2, r0 @ encoding: [0x00,0x00,0x92,0xe0]
; CHECK: adc r1, r3, r1 @ encoding: [0x01,0x10,0xa3,0xe0] ; CHECK: adc r1, r3, r1 @ encoding: [0x01,0x10,0xa3,0xe0]
@ -71,7 +65,6 @@ entry:
} }
define i32 @f7(i32 %a, i32 %b) { define i32 @f7(i32 %a, i32 %b) {
entry:
; CHECK: f7 ; CHECK: f7
; CHECK: uxtab r0, r0, r1 @ encoding: [0x71,0x00,0xe0,0xe6] ; CHECK: uxtab r0, r0, r1 @ encoding: [0x71,0x00,0xe0,0xe6]
%and = and i32 %b, 255 %and = and i32 %b, 255
@ -80,7 +73,6 @@ entry:
} }
define i32 @f8(i32 %a) { define i32 @f8(i32 %a) {
entry:
; CHECK: f8 ; CHECK: f8
; CHECK: movt r0, #42405 @ encoding: [0xa5,0x05,0x4a,0xe3] ; CHECK: movt r0, #42405 @ encoding: [0xa5,0x05,0x4a,0xe3]
%and = and i32 %a, 65535 %and = and i32 %a, 65535
@ -89,14 +81,12 @@ entry:
} }
define i32 @f9() { define i32 @f9() {
entry:
; CHECK: f9 ; CHECK: f9
; CHECK: movw r0, #42405 @ encoding: [0xa5,0x05,0x0a,0xe3] ; CHECK: movw r0, #42405 @ encoding: [0xa5,0x05,0x0a,0xe3]
ret i32 42405 ret i32 42405
} }
define i64 @f10(i64 %a) { define i64 @f10(i64 %a) {
entry:
; CHECK: f10 ; CHECK: f10
; CHECK: asrs r1, r1, #1 @ encoding: [0xc1,0x10,0xb0,0xe1] ; CHECK: asrs r1, r1, #1 @ encoding: [0xc1,0x10,0xb0,0xe1]
; CHECK: rrx r0, r0 @ encoding: [0x60,0x00,0xa0,0xe1] ; CHECK: rrx r0, r0 @ encoding: [0x60,0x00,0xa0,0xe1]
@ -105,16 +95,15 @@ entry:
} }
define i32 @f11([1 x i32] %A.coerce0, [1 x i32] %B.coerce0) { define i32 @f11([1 x i32] %A.coerce0, [1 x i32] %B.coerce0) {
entry:
; CHECK: f11 ; CHECK: f11
; CHECK: ubfx r1, r1, #8, #5 @ encoding: [0x51,0x14,0xe4,0xe7] ; CHECK: ubfx r1, r1, #8, #5 @ encoding: [0x51,0x14,0xe4,0xe7]
; CHECK: sbfx r0, r0, #13, #7 @ encoding: [0xd0,0x06,0xa6,0xe7] ; CHECK: sbfx r0, r0, #13, #7 @ encoding: [0xd0,0x06,0xa6,0xe7]
%tmp11 = extractvalue [1 x i32] %A.coerce0, 0 %tmp1 = extractvalue [1 x i32] %A.coerce0, 0
%tmp4 = extractvalue [1 x i32] %B.coerce0, 0 %tmp2 = extractvalue [1 x i32] %B.coerce0, 0
%0 = shl i32 %tmp11, 12 %tmp3 = shl i32 %tmp1, 12
%bf.val.sext = ashr i32 %0, 25 %bf.val.sext = ashr i32 %tmp3, 25
%1 = lshr i32 %tmp4, 8 %tmp4 = lshr i32 %tmp2, 8
%bf.clear2 = and i32 %1, 31 %bf.clear2 = and i32 %tmp4, 31
%mul = mul nsw i32 %bf.val.sext, %bf.clear2 %mul = mul nsw i32 %bf.val.sext, %bf.clear2
ret i32 %mul ret i32 %mul
} }
@ -130,7 +119,6 @@ define i64 @f13() {
; CHECK: f13: ; CHECK: f13:
; CHECK: mvn r0, #0 @ encoding: [0x00,0x00,0xe0,0xe3] ; CHECK: mvn r0, #0 @ encoding: [0x00,0x00,0xe0,0xe3]
; CHECK: mvn r1, #2, 2 @ encoding: [0x02,0x11,0xe0,0xe3] ; CHECK: mvn r1, #2, 2 @ encoding: [0x02,0x11,0xe0,0xe3]
entry:
ret i64 9223372036854775807 ret i64 9223372036854775807
} }
@ -225,16 +213,16 @@ define i32 @f22(i32 %X, i32 %Y) {
; CHECK: f22 ; CHECK: f22
; CHECK: pkhtb r0, r0, r1, asr #22 @ encoding: [0x51,0x0b,0x80,0xe6] ; CHECK: pkhtb r0, r0, r1, asr #22 @ encoding: [0x51,0x0b,0x80,0xe6]
%tmp1 = and i32 %X, -65536 %tmp1 = and i32 %X, -65536
%tmp3 = lshr i32 %Y, 22 %tmp2 = lshr i32 %Y, 22
%tmp57 = or i32 %tmp3, %tmp1 %tmp3 = or i32 %tmp2, %tmp1
ret i32 %tmp57 ret i32 %tmp3
} }
define i32 @f23(i32 %X, i32 %Y) { define i32 @f23(i32 %X, i32 %Y) {
; CHECK: f23 ; CHECK: f23
; CHECK: pkhbt r0, r0, r1, lsl #18 @ encoding: [0x11,0x09,0x80,0xe6] ; CHECK: pkhbt r0, r0, r1, lsl #18 @ encoding: [0x11,0x09,0x80,0xe6]
%tmp19 = and i32 %X, 65535 %tmp1 = and i32 %X, 65535
%tmp37 = shl i32 %Y, 18 %tmp2 = shl i32 %Y, 18
%tmp5 = or i32 %tmp37, %tmp19 %tmp3 = or i32 %tmp1, %tmp2
ret i32 %tmp5 ret i32 %tmp3
} }