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[lldb] [debugserver] Add stN aliases for stmmN for compatibility 

Add stN aliases for the FPU (stmmN) registers on MacOSX.  This should
improve compatibility between MacOSX and other platforms, and partially
fix x86*-fp-write tests without having to duplicate them.  Note that
the tests are currently still broken due to ftag incompatibility.

Differential Revision: https://reviews.llvm.org/D91847
This commit is contained in:
Michał Górny 2020-11-20 09:44:33 +01:00
parent 3a60a1f165
commit b9bfe8a753
7 changed files with 59 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lldb/test/API/commands/register/register/register_command/TestRegisters.py
View File

@ -320,10 +320,12 @@ class RegisterCommandsTestCase(TestBase):
]
st0regname = None
if currentFrame.FindRegister("st0").IsValid():
st0regname = "st0"
elif currentFrame.FindRegister("stmm0").IsValid():
# Darwin is using stmmN by default but support stN as an alias.
# Therefore, we need to check for stmmN first.
if currentFrame.FindRegister("stmm0").IsValid():
st0regname = "stmm0"
elif currentFrame.FindRegister("st0").IsValid():
st0regname = "st0"
if st0regname is not None:
# reg value
# must-have

1
lldb/test/CMakeLists.txt
View File

@ -166,6 +166,7 @@ llvm_canonicalize_cmake_booleans(
LLDB_ENABLE_LZMA
LLVM_ENABLE_ZLIB
LLVM_ENABLE_SHARED_LIBS
LLDB_USE_SYSTEM_DEBUGSERVER
LLDB_IS_64_BITS)
# Configure the individual test suites.

2
lldb/test/Shell/Register/x86-multithread-write.test
View File

@ -1,6 +1,6 @@
# XFAIL: system-windows
# XFAIL: system-darwin
# REQUIRES: native && (target-x86 || target-x86_64)
# UNSUPPORTED: system-debugserver
# RUN: %clangxx_host %p/Inputs/x86-multithread-write.cpp -o %t -pthread
# RUN: %lldb -b -s %s %t | FileCheck %s

3
lldb/test/Shell/lit.cfg.py
View File

@ -120,6 +120,9 @@ if config.lldb_enable_lzma:
if find_executable('xz') != None:
config.available_features.add('xz')
if config.lldb_system_debugserver:
config.available_features.add('system-debugserver')
# NetBSD permits setting dbregs either if one is root
# or if user_set_dbregs is enabled
can_set_dbregs = True

1
lldb/test/Shell/lit.site.cfg.py.in
View File

@ -22,6 +22,7 @@ config.lldb_bitness = 64 if @LLDB_IS_64_BITS@ else 32
config.lldb_enable_python = @LLDB_ENABLE_PYTHON@
config.lldb_enable_lua = @LLDB_ENABLE_LUA@
config.lldb_build_directory = "@LLDB_TEST_BUILD_DIRECTORY@"
config.lldb_system_debugserver = @LLDB_USE_SYSTEM_DEBUGSERVER@
# The shell tests use their own module caches.
config.lldb_module_cache = os.path.join("@LLDB_TEST_MODULE_CACHE_LLDB@", "lldb-shell")
config.clang_module_cache = os.path.join("@LLDB_TEST_MODULE_CACHE_CLANG@", "lldb-shell")

48
lldb/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp
View File

@ -1356,28 +1356,28 @@ const DNBRegisterInfo DNBArchImplI386::g_fpu_registers_no_avx[] = {
FPU_SIZE_UINT(mxcsrmask), FPU_OFFSET(mxcsrmask), INVALID_NUB_REGNUM,
INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
{e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm0, "stmm0", "st0", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm0), FPU_OFFSET(stmm0), INVALID_NUB_REGNUM, dwarf_stmm0,
INVALID_NUB_REGNUM, debugserver_stmm0, NULL, NULL},
{e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm1, "stmm1", "st1", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm1), FPU_OFFSET(stmm1), INVALID_NUB_REGNUM, dwarf_stmm1,
INVALID_NUB_REGNUM, debugserver_stmm1, NULL, NULL},
{e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm2, "stmm2", "st2", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm2), FPU_OFFSET(stmm2), INVALID_NUB_REGNUM, dwarf_stmm2,
INVALID_NUB_REGNUM, debugserver_stmm2, NULL, NULL},
{e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm3, "stmm3", "st3", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm3), FPU_OFFSET(stmm3), INVALID_NUB_REGNUM, dwarf_stmm3,
INVALID_NUB_REGNUM, debugserver_stmm3, NULL, NULL},
{e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm4, "stmm4", "st4", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm4), FPU_OFFSET(stmm4), INVALID_NUB_REGNUM, dwarf_stmm4,
INVALID_NUB_REGNUM, debugserver_stmm4, NULL, NULL},
{e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm5, "stmm5", "st5", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm5), FPU_OFFSET(stmm5), INVALID_NUB_REGNUM, dwarf_stmm5,
INVALID_NUB_REGNUM, debugserver_stmm5, NULL, NULL},
{e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm6, "stmm6", "st6", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm6), FPU_OFFSET(stmm6), INVALID_NUB_REGNUM, dwarf_stmm6,
INVALID_NUB_REGNUM, debugserver_stmm6, NULL, NULL},
{e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm7, "stmm7", "st7", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm7), FPU_OFFSET(stmm7), INVALID_NUB_REGNUM, dwarf_stmm7,
INVALID_NUB_REGNUM, debugserver_stmm7, NULL, NULL},
@ -1447,28 +1447,28 @@ const DNBRegisterInfo DNBArchImplI386::g_fpu_registers_avx[] = {
FPU_SIZE_UINT(mxcsrmask), AVX_OFFSET(mxcsrmask), INVALID_NUB_REGNUM,
INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
{e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm0, "stmm0", "st0", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), INVALID_NUB_REGNUM, dwarf_stmm0,
INVALID_NUB_REGNUM, debugserver_stmm0, NULL, NULL},
{e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm1, "stmm1", "st1", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), INVALID_NUB_REGNUM, dwarf_stmm1,
INVALID_NUB_REGNUM, debugserver_stmm1, NULL, NULL},
{e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm2, "stmm2", "st2", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), INVALID_NUB_REGNUM, dwarf_stmm2,
INVALID_NUB_REGNUM, debugserver_stmm2, NULL, NULL},
{e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm3, "stmm3", "st3", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), INVALID_NUB_REGNUM, dwarf_stmm3,
INVALID_NUB_REGNUM, debugserver_stmm3, NULL, NULL},
{e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm4, "stmm4", "st4", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), INVALID_NUB_REGNUM, dwarf_stmm4,
INVALID_NUB_REGNUM, debugserver_stmm4, NULL, NULL},
{e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm5, "stmm5", "st5", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), INVALID_NUB_REGNUM, dwarf_stmm5,
INVALID_NUB_REGNUM, debugserver_stmm5, NULL, NULL},
{e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm6, "stmm6", "st6", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), INVALID_NUB_REGNUM, dwarf_stmm6,
INVALID_NUB_REGNUM, debugserver_stmm6, NULL, NULL},
{e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm7, "stmm7", "st7", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), INVALID_NUB_REGNUM, dwarf_stmm7,
INVALID_NUB_REGNUM, debugserver_stmm7, NULL, NULL},
@ -1596,28 +1596,28 @@ const DNBRegisterInfo DNBArchImplI386::g_fpu_registers_avx512f[] = {
FPU_SIZE_UINT(mxcsrmask), AVX_OFFSET(mxcsrmask), INVALID_NUB_REGNUM,
INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
{e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm0, "stmm0", "st0", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), INVALID_NUB_REGNUM, dwarf_stmm0,
INVALID_NUB_REGNUM, debugserver_stmm0, NULL, NULL},
{e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm1, "stmm1", "st1", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), INVALID_NUB_REGNUM, dwarf_stmm1,
INVALID_NUB_REGNUM, debugserver_stmm1, NULL, NULL},
{e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm2, "stmm2", "st2", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), INVALID_NUB_REGNUM, dwarf_stmm2,
INVALID_NUB_REGNUM, debugserver_stmm2, NULL, NULL},
{e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm3, "stmm3", "st3", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), INVALID_NUB_REGNUM, dwarf_stmm3,
INVALID_NUB_REGNUM, debugserver_stmm3, NULL, NULL},
{e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm4, "stmm4", "st4", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), INVALID_NUB_REGNUM, dwarf_stmm4,
INVALID_NUB_REGNUM, debugserver_stmm4, NULL, NULL},
{e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm5, "stmm5", "st5", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), INVALID_NUB_REGNUM, dwarf_stmm5,
INVALID_NUB_REGNUM, debugserver_stmm5, NULL, NULL},
{e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm6, "stmm6", "st6", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), INVALID_NUB_REGNUM, dwarf_stmm6,
INVALID_NUB_REGNUM, debugserver_stmm6, NULL, NULL},
{e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm7, "stmm7", "st7", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), INVALID_NUB_REGNUM, dwarf_stmm7,
INVALID_NUB_REGNUM, debugserver_stmm7, NULL, NULL},

48
lldb/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp
View File

@ -1767,28 +1767,28 @@ const DNBRegisterInfo DNBArchImplX86_64::g_fpu_registers_no_avx[] = {
FPU_SIZE_UINT(mxcsrmask), FPU_OFFSET(mxcsrmask), -1U, -1U, -1U, -1U, NULL,
NULL},
{e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm0, "stmm0", "st0", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm0), FPU_OFFSET(stmm0), ehframe_dwarf_stmm0,
ehframe_dwarf_stmm0, -1U, debugserver_stmm0, NULL, NULL},
{e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm1, "stmm1", "st1", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm1), FPU_OFFSET(stmm1), ehframe_dwarf_stmm1,
ehframe_dwarf_stmm1, -1U, debugserver_stmm1, NULL, NULL},
{e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm2, "stmm2", "st2", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm2), FPU_OFFSET(stmm2), ehframe_dwarf_stmm2,
ehframe_dwarf_stmm2, -1U, debugserver_stmm2, NULL, NULL},
{e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm3, "stmm3", "st3", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm3), FPU_OFFSET(stmm3), ehframe_dwarf_stmm3,
ehframe_dwarf_stmm3, -1U, debugserver_stmm3, NULL, NULL},
{e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm4, "stmm4", "st4", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm4), FPU_OFFSET(stmm4), ehframe_dwarf_stmm4,
ehframe_dwarf_stmm4, -1U, debugserver_stmm4, NULL, NULL},
{e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm5, "stmm5", "st5", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm5), FPU_OFFSET(stmm5), ehframe_dwarf_stmm5,
ehframe_dwarf_stmm5, -1U, debugserver_stmm5, NULL, NULL},
{e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm6, "stmm6", "st6", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm6), FPU_OFFSET(stmm6), ehframe_dwarf_stmm6,
ehframe_dwarf_stmm6, -1U, debugserver_stmm6, NULL, NULL},
{e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm7, "stmm7", "st7", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm7), FPU_OFFSET(stmm7), ehframe_dwarf_stmm7,
ehframe_dwarf_stmm7, -1U, debugserver_stmm7, NULL, NULL},
@ -1882,28 +1882,28 @@ const DNBRegisterInfo DNBArchImplX86_64::g_fpu_registers_avx[] = {
FPU_SIZE_UINT(mxcsrmask), AVX_OFFSET(mxcsrmask), -1U, -1U, -1U, -1U, NULL,
NULL},
{e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm0, "stmm0", "st0", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), ehframe_dwarf_stmm0,
ehframe_dwarf_stmm0, -1U, debugserver_stmm0, NULL, NULL},
{e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm1, "stmm1", "st1", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), ehframe_dwarf_stmm1,
ehframe_dwarf_stmm1, -1U, debugserver_stmm1, NULL, NULL},
{e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm2, "stmm2", "st2", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), ehframe_dwarf_stmm2,
ehframe_dwarf_stmm2, -1U, debugserver_stmm2, NULL, NULL},
{e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm3, "stmm3", "st3", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), ehframe_dwarf_stmm3,
ehframe_dwarf_stmm3, -1U, debugserver_stmm3, NULL, NULL},
{e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm4, "stmm4", "st4", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), ehframe_dwarf_stmm4,
ehframe_dwarf_stmm4, -1U, debugserver_stmm4, NULL, NULL},
{e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm5, "stmm5", "st5", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), ehframe_dwarf_stmm5,
ehframe_dwarf_stmm5, -1U, debugserver_stmm5, NULL, NULL},
{e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm6, "stmm6", "st6", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), ehframe_dwarf_stmm6,
ehframe_dwarf_stmm6, -1U, debugserver_stmm6, NULL, NULL},
{e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm7, "stmm7", "st7", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), ehframe_dwarf_stmm7,
ehframe_dwarf_stmm7, -1U, debugserver_stmm7, NULL, NULL},
@ -2080,28 +2080,28 @@ const DNBRegisterInfo DNBArchImplX86_64::g_fpu_registers_avx512f[] = {
FPU_SIZE_UINT(mxcsrmask), AVX_OFFSET(mxcsrmask), -1U, -1U, -1U, -1U, NULL,
NULL},
{e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm0, "stmm0", "st0", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), ehframe_dwarf_stmm0,
ehframe_dwarf_stmm0, -1U, debugserver_stmm0, NULL, NULL},
{e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm1, "stmm1", "st1", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), ehframe_dwarf_stmm1,
ehframe_dwarf_stmm1, -1U, debugserver_stmm1, NULL, NULL},
{e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm2, "stmm2", "st2", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), ehframe_dwarf_stmm2,
ehframe_dwarf_stmm2, -1U, debugserver_stmm2, NULL, NULL},
{e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm3, "stmm3", "st3", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), ehframe_dwarf_stmm3,
ehframe_dwarf_stmm3, -1U, debugserver_stmm3, NULL, NULL},
{e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm4, "stmm4", "st4", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), ehframe_dwarf_stmm4,
ehframe_dwarf_stmm4, -1U, debugserver_stmm4, NULL, NULL},
{e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm5, "stmm5", "st5", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), ehframe_dwarf_stmm5,
ehframe_dwarf_stmm5, -1U, debugserver_stmm5, NULL, NULL},
{e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm6, "stmm6", "st6", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), ehframe_dwarf_stmm6,
ehframe_dwarf_stmm6, -1U, debugserver_stmm6, NULL, NULL},
{e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
{e_regSetFPU, fpu_stmm7, "stmm7", "st7", Vector, VectorOfUInt8,
FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), ehframe_dwarf_stmm7,
ehframe_dwarf_stmm7, -1U, debugserver_stmm7, NULL, NULL},