[X86] Mark LDS/LES as not being allowed in 64-bit mode.
Their opcodes are used as part of the VEX prefix in 64-bit mode. Clearly the disassembler implicitly decoded them as AVX instructions in 64-bit mode, but I think the AsmParser would have encoded them. llvm-svn: 258793
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			@ -339,9 +339,11 @@ def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
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def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
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                "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
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                "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
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                Requires<[Not64BitMode]>;
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def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
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                "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
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                "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
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                Requires<[Not64BitMode]>;
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def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
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                "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
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			@ -351,9 +353,11 @@ def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
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                 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
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def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
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                "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
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                "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16,
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                Requires<[Not64BitMode]>;
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def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
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                "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
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                "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32,
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                Requires<[Not64BitMode]>;
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def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
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                "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
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