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AMDGPU: Remove unused MachineFunctionInfo fields 

These were leftovers from a half-implement spill to LDS attempt.
This commit is contained in:
Matt Arsenault 2022-04-15 23:09:03 -04:00
parent 8591328e15
commit bc7902f148
2 changed files with 1 additions and 15 deletions
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5
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
View File

@ -875,10 +875,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
LDSAlignShift = 9; LDSAlignShift = 9;
} }
unsigned LDSSpillSize = ProgInfo.LDSSize = MFI->getLDSSize();
MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
ProgInfo.LDSBlocks = ProgInfo.LDSBlocks =
alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift; alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;

11
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
View File

@ -335,8 +335,6 @@ template <> struct MappingTraits<SIMachineFunctionInfo> {
class SIMachineFunctionInfo final : public AMDGPUMachineFunction { class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
friend class GCNTargetMachine; friend class GCNTargetMachine;
Register TIDReg = AMDGPU::NoRegister;
// Registers that may be reserved for spilling purposes. These may be the same // Registers that may be reserved for spilling purposes. These may be the same
// as the input registers. // as the input registers.
Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG; Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
@ -382,7 +380,6 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
std::unique_ptr<const AMDGPUGWSResourcePseudoSourceValue> GWSResourcePSV; std::unique_ptr<const AMDGPUGWSResourcePseudoSourceValue> GWSResourcePSV;
private: private:
unsigned LDSWaveSpillSize = 0;
unsigned NumUserSGPRs = 0; unsigned NumUserSGPRs = 0;
unsigned NumSystemSGPRs = 0; unsigned NumSystemSGPRs = 0;
@ -569,10 +566,6 @@ public:
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI); int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI);
Optional<int> getOptionalScavengeFI() const { return ScavengeFI; } Optional<int> getOptionalScavengeFI() const { return ScavengeFI; }
bool hasCalculatedTID() const { return TIDReg != 0; };
Register getTIDReg() const { return TIDReg; };
void setTIDReg(Register Reg) { TIDReg = Reg; }
unsigned getBytesInStackArgArea() const { unsigned getBytesInStackArgArea() const {
return BytesInStackArgArea; return BytesInStackArgArea;
} }
@ -912,10 +905,6 @@ public:
llvm_unreachable("unexpected dimension"); llvm_unreachable("unexpected dimension");
} }
unsigned getLDSWaveSpillSize() const {
return LDSWaveSpillSize;
}
const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII) { const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII) {
if (!BufferPSV) if (!BufferPSV)
BufferPSV = std::make_unique<AMDGPUBufferPseudoSourceValue>(TII); BufferPSV = std::make_unique<AMDGPUBufferPseudoSourceValue>(TII);