From bcec0f27a2c37b64d5e8b84bbbfa563edae6affe Mon Sep 17 00:00:00 2001 From: Joe Nash Date: Mon, 4 Jan 2021 19:47:55 -0500 Subject: [PATCH] [AMDGPU] Deduplicate VOP tablegen asm & ins VOP3 and VOP DPP subroutines to generate input operands and asm strings were essentially copy pasted several times. They are deduplicated to reduce the maintenance burden and allow faster development. Reviewed By: dp Differential Revision: https://reviews.llvm.org/D94102 Change-Id: I76225eed3c33239d9573351e0c8a0abfad0146ea --- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 195 +++++++-------------- llvm/lib/Target/AMDGPU/VOP3Instructions.td | 1 + 2 files changed, 67 insertions(+), 129 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index e48138e56d71..78600bebdad2 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1587,7 +1587,7 @@ class getIns32 { // Returns the input arguments for VOP3 instructions for the given SrcVT. class getIns64 { dag ret = @@ -1602,7 +1602,7 @@ class getIns64 { + // getInst64 handles clamp and omod. implicit mutex between vop3p and omod + dag base = getIns64 .ret; + dag opsel = (ins op_sel0:$op_sel); + dag vop3pFields = (ins op_sel_hi0:$op_sel_hi, neg_lo0:$neg_lo, neg_hi0:$neg_hi); + dag ret = !con(base, + !if(HasOpSel, opsel,(ins)), + !if(IsVOP3P, vop3pFields,(ins))); +} -// The modifiers (except clamp) are dummy operands for the benefit of -// printing and parsing. They defer their values to looking at the -// srcN_modifiers for what to print. class getInsVOP3P { - dag ret = !if (!eq(NumSrcArgs, 2), - !if (HasClamp, - (ins Src0Mod:$src0_modifiers, Src0RC:$src0, - Src1Mod:$src1_modifiers, Src1RC:$src1, - clampmod0:$clamp, - op_sel0:$op_sel, op_sel_hi0:$op_sel_hi, - neg_lo0:$neg_lo, neg_hi0:$neg_hi), - (ins Src0Mod:$src0_modifiers, Src0RC:$src0, - Src1Mod:$src1_modifiers, Src1RC:$src1, - op_sel0:$op_sel, op_sel_hi0:$op_sel_hi, - neg_lo0:$neg_lo, neg_hi0:$neg_hi)), - // else NumSrcArgs == 3 - !if (HasClamp, - (ins Src0Mod:$src0_modifiers, Src0RC:$src0, - Src1Mod:$src1_modifiers, Src1RC:$src1, - Src2Mod:$src2_modifiers, Src2RC:$src2, - clampmod0:$clamp, - op_sel0:$op_sel, op_sel_hi0:$op_sel_hi, - neg_lo0:$neg_lo, neg_hi0:$neg_hi), - (ins Src0Mod:$src0_modifiers, Src0RC:$src0, - Src1Mod:$src1_modifiers, Src1RC:$src1, - Src2Mod:$src2_modifiers, Src2RC:$src2, - op_sel0:$op_sel, op_sel_hi0:$op_sel_hi, - neg_lo0:$neg_lo, neg_hi0:$neg_hi)) - ); + dag ret = getInsVOP3Base.ret; } -class getInsVOP3OpSel { - dag ret = !if (!eq(NumSrcArgs, 2), - !if (HasClamp, - (ins Src0Mod:$src0_modifiers, Src0RC:$src0, - Src1Mod:$src1_modifiers, Src1RC:$src1, - clampmod0:$clamp, - op_sel0:$op_sel), - (ins Src0Mod:$src0_modifiers, Src0RC:$src0, - Src1Mod:$src1_modifiers, Src1RC:$src1, - op_sel0:$op_sel)), - // else NumSrcArgs == 3 - !if (HasClamp, - (ins Src0Mod:$src0_modifiers, Src0RC:$src0, - Src1Mod:$src1_modifiers, Src1RC:$src1, - Src2Mod:$src2_modifiers, Src2RC:$src2, - clampmod0:$clamp, - op_sel0:$op_sel), - (ins Src0Mod:$src0_modifiers, Src0RC:$src0, - Src1Mod:$src1_modifiers, Src1RC:$src1, - Src2Mod:$src2_modifiers, Src2RC:$src2, - op_sel0:$op_sel)) - ); +class getInsVOP3OpSel { + dag ret = getInsVOP3Base.ret; } -class getInsDPP { dag ret = !if (!eq(NumSrcArgs, 0), // VOP1 without input operands (V_NOP) - (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, - bank_mask:$bank_mask, bound_ctrl:$bound_ctrl), + (ins ), !if (!eq(NumSrcArgs, 1), !if (HasModifiers, // VOP1_DPP with modifiers (ins DstRC:$old, Src0Mod:$src0_modifiers, - Src0RC:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, - bank_mask:$bank_mask, bound_ctrl:$bound_ctrl) + Src0RC:$src0) /* else */, // VOP1_DPP without modifiers - (ins DstRC:$old, Src0RC:$src0, - dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, - bank_mask:$bank_mask, bound_ctrl:$bound_ctrl) - /* endif */) - /* NumSrcArgs == 2 */, + (ins DstRC:$old, Src0RC:$src0) + /* endif */), !if (HasModifiers, // VOP2_DPP with modifiers (ins DstRC:$old, Src0Mod:$src0_modifiers, Src0RC:$src0, - Src1Mod:$src1_modifiers, Src1RC:$src1, - dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, - bank_mask:$bank_mask, bound_ctrl:$bound_ctrl) + Src1Mod:$src1_modifiers, Src1RC:$src1) /* else */, // VOP2_DPP without modifiers (ins DstRC:$old, - Src0RC:$src0, Src1RC:$src1, dpp_ctrl:$dpp_ctrl, - row_mask:$row_mask, bank_mask:$bank_mask, - bound_ctrl:$bound_ctrl) - /* endif */))); + Src0RC:$src0, Src1RC:$src1) + ))); +} + +class getInsDPP { + dag ret = !con(getInsDPPBase.ret, + (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, + bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)); } class getInsDPP16 { + int NumSrcArgs, bit HasModifiers, + Operand Src0Mod, Operand Src1Mod> { dag ret = !con(getInsDPP.ret, (ins FI:$fi)); @@ -1775,30 +1743,9 @@ class getInsDPP16 { - dag ret = !if (!eq(NumSrcArgs, 0), - // VOP1 without input operands (V_NOP) - (ins dpp8:$dpp8, FI:$fi), - !if (!eq(NumSrcArgs, 1), - !if (HasModifiers, - // VOP1_DPP with modifiers - (ins DstRC:$old, Src0Mod:$src0_modifiers, - Src0RC:$src0, dpp8:$dpp8, FI:$fi) - /* else */, - // VOP1_DPP without modifiers - (ins DstRC:$old, Src0RC:$src0, dpp8:$dpp8, FI:$fi) - /* endif */) - /* NumSrcArgs == 2 */, - !if (HasModifiers, - // VOP2_DPP with modifiers - (ins DstRC:$old, - Src0Mod:$src0_modifiers, Src0RC:$src0, - Src1Mod:$src1_modifiers, Src1RC:$src1, - dpp8:$dpp8, FI:$fi) - /* else */, - // VOP2_DPP without modifiers - (ins DstRC:$old, - Src0RC:$src0, Src1RC:$src1, dpp8:$dpp8, FI:$fi) - /* endif */))); + dag ret = !con(getInsDPPBase.ret, + (ins dpp8:$dpp8, FI:$fi)); } @@ -1916,6 +1863,7 @@ class getAsmVOP3P { @@ -1962,22 +1910,12 @@ class getAsmDPP16 .ret#"$fi"; } -class getAsmDPP8 { - string dst = !if(HasDst, - !if(!eq(DstVT.Size, 1), - "$sdst", - "$vdst"), - ""); // use $sdst for VOPC - string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,"); - string src1 = !if(!eq(NumSrcArgs, 1), "", - !if(!eq(NumSrcArgs, 2), " $src1_modifiers", - " $src1_modifiers,")); - string args = !if(!not(HasModifiers), - getAsm32<0, NumSrcArgs, DstVT>.ret, - ", "#src0#src1); - string ret = dst#args#" $dpp8$fi"; +class getAsmDPP8 + : getAsmDPP { + let ret = dst#args#" $dpp8$fi"; } + class getAsmSDWA { string dst = !if(HasDst, !if(!eq(DstVT.Size, 1), @@ -2167,11 +2105,10 @@ class VOPProfile _ArgVT, bit _EnableF32SrcMods = 0, NumSrcArgs, HasClamp, Src0PackedMod, Src1PackedMod, Src2PackedMod>.ret; field dag InsVOP3OpSel = getInsVOP3OpSel.ret, - getOpSelMod.ret, - getOpSelMod.ret>.ret; + NumSrcArgs, HasClamp, HasOMod, + getOpSelMod.ret, + getOpSelMod.ret, + getOpSelMod.ret>.ret; field dag InsDPP = !if(HasExtDPP, getInsDPP.ret, @@ -2189,7 +2126,7 @@ class VOPProfile _ArgVT, bit _EnableF32SrcMods = 0, field string Asm64 = getAsm64.ret; field string AsmVOP3P = getAsmVOP3P.ret; field string AsmVOP3OpSel = getAsmVOP3OpSel.ret; diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td index f349a0f54fa7..9bdcdd376269 100644 --- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -182,6 +182,7 @@ class VOP3_Profile : VOPProf " " # !if(Features.HasOpSel, getAsmVOP3OpSel.ret,