[NFC][DAGCombine][X86][AArch64] Tests for 'A - (A & (B - 1))' pattern (PR44448)
https://rise4fun.com/Alive/ZVdp Name: ptr - (ptr & (alignment-1)) -> ptr & (0 - alignment) %mask = add i64 %alignment, -1 %bias = and i64 %ptr, %mask %r = sub i64 %ptr, %bias => %highbitmask = sub i64 0, %alignment %r = and i64 %ptr, %highbitmask The main motivational pattern involes pointer-typed values, so this transform can't really be done in middle-end. See https://bugs.llvm.org/show_bug.cgi?id=44448 https://reviews.llvm.org/D71499
This commit is contained in:
Roman Lebedev
parent
2e03324441
commit
c0cbe3fbb7
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@ -0,0 +1,153 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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; Fold
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; ptr - (ptr & (alignment-1))
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; To
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; ptr & (0 - alignment)
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;
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; This needs to be a backend-level fold because only by now pointers
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; are just registers; in middle-end IR this can only be done via @llvm.ptrmask()
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; intrinsic which is not sufficiently widely-spread yet.
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;
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; https://bugs.llvm.org/show_bug.cgi?id=44448
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; The basic positive tests
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define i32 @t0_32(i32 %ptr, i32 %alignment) nounwind {
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; CHECK-LABEL: t0_32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub w8, w1, #1 // =1
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; CHECK-NEXT: and w8, w0, w8
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; CHECK-NEXT: sub w0, w0, w8
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; CHECK-NEXT: ret
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%mask = add i32 %alignment, -1
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%bias = and i32 %ptr, %mask
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%r = sub i32 %ptr, %bias
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ret i32 %r
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}
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define i64 @t1_64(i64 %ptr, i64 %alignment) nounwind {
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; CHECK-LABEL: t1_64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub x8, x1, #1 // =1
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; CHECK-NEXT: and x8, x0, x8
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; CHECK-NEXT: sub x0, x0, x8
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; CHECK-NEXT: ret
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%mask = add i64 %alignment, -1
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%bias = and i64 %ptr, %mask
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%r = sub i64 %ptr, %bias
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ret i64 %r
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}
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define i32 @t2_commutative(i32 %ptr, i32 %alignment) nounwind {
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; CHECK-LABEL: t2_commutative:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub w8, w1, #1 // =1
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; CHECK-NEXT: and w8, w8, w0
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; CHECK-NEXT: sub w0, w0, w8
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; CHECK-NEXT: ret
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%mask = add i32 %alignment, -1
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%bias = and i32 %mask, %ptr ; swapped
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%r = sub i32 %ptr, %bias
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ret i32 %r
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}
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; Extra use tests
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define i32 @t3_extrause0(i32 %ptr, i32 %alignment, i32* %mask_storage) nounwind {
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; CHECK-LABEL: t3_extrause0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub w8, w1, #1 // =1
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; CHECK-NEXT: and w9, w0, w8
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; CHECK-NEXT: sub w0, w0, w9
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; CHECK-NEXT: str w8, [x2]
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; CHECK-NEXT: ret
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%mask = add i32 %alignment, -1
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store i32 %mask, i32* %mask_storage
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%bias = and i32 %ptr, %mask
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%r = sub i32 %ptr, %bias
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ret i32 %r
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}
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define i32 @n4_extrause1(i32 %ptr, i32 %alignment, i32* %bias_storage) nounwind {
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; CHECK-LABEL: n4_extrause1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub w8, w1, #1 // =1
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; CHECK-NEXT: and w8, w0, w8
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; CHECK-NEXT: sub w0, w0, w8
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; CHECK-NEXT: str w8, [x2]
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; CHECK-NEXT: ret
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%mask = add i32 %alignment, -1
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%bias = and i32 %ptr, %mask ; has extra uses, can't fold
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store i32 %bias, i32* %bias_storage
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%r = sub i32 %ptr, %bias
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ret i32 %r
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}
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define i32 @n5_extrause2(i32 %ptr, i32 %alignment, i32* %mask_storage, i32* %bias_storage) nounwind {
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; CHECK-LABEL: n5_extrause2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub w8, w1, #1 // =1
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; CHECK-NEXT: str w8, [x2]
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; CHECK-NEXT: and w8, w0, w8
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; CHECK-NEXT: sub w0, w0, w8
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; CHECK-NEXT: str w8, [x3]
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; CHECK-NEXT: ret
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%mask = add i32 %alignment, -1
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store i32 %mask, i32* %mask_storage
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%bias = and i32 %ptr, %mask ; has extra uses, can't fold
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store i32 %bias, i32* %bias_storage
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%r = sub i32 %ptr, %bias
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ret i32 %r
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}
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; Negative tests
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define i32 @n6_different_ptrs(i32 %ptr0, i32 %ptr1, i32 %alignment) nounwind {
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; CHECK-LABEL: n6_different_ptrs:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub w8, w2, #1 // =1
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; CHECK-NEXT: and w8, w1, w8
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; CHECK-NEXT: sub w0, w0, w8
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; CHECK-NEXT: ret
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%mask = add i32 %alignment, -1
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%bias = and i32 %ptr1, %mask ; not %ptr0
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%r = sub i32 %ptr0, %bias ; not %ptr1
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ret i32 %r
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}
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define i32 @n7_different_ptrs_commutative(i32 %ptr0, i32 %ptr1, i32 %alignment) nounwind {
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; CHECK-LABEL: n7_different_ptrs_commutative:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub w8, w2, #1 // =1
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; CHECK-NEXT: and w8, w8, w1
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; CHECK-NEXT: sub w0, w0, w8
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; CHECK-NEXT: ret
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%mask = add i32 %alignment, -1
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%bias = and i32 %mask, %ptr1 ; swapped, not %ptr0
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%r = sub i32 %ptr0, %bias ; not %ptr1
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ret i32 %r
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}
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define i32 @n8_not_lowbit_mask(i32 %ptr, i32 %alignment) nounwind {
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; CHECK-LABEL: n8_not_lowbit_mask:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w1, #1 // =1
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; CHECK-NEXT: and w8, w0, w8
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; CHECK-NEXT: sub w0, w0, w8
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; CHECK-NEXT: ret
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%mask = add i32 %alignment, 1 ; not -1
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%bias = and i32 %ptr, %mask
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%r = sub i32 %ptr, %bias
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ret i32 %r
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}
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define i32 @n9_sub_is_not_commutative(i32 %ptr, i32 %alignment) nounwind {
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; CHECK-LABEL: n9_sub_is_not_commutative:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub w8, w1, #1 // =1
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; CHECK-NEXT: and w8, w0, w8
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; CHECK-NEXT: sub w0, w8, w0
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; CHECK-NEXT: ret
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%mask = add i32 %alignment, -1
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%bias = and i32 %ptr, %mask
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%r = sub i32 %bias, %ptr ; wrong order
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ret i32 %r
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}
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@ -0,0 +1,271 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=i686-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,X64
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; Fold
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; ptr - (ptr & (alignment-1))
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; To
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; ptr & (0 - alignment)
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;
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; This needs to be a backend-level fold because only by now pointers
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; are just registers; in middle-end IR this can only be done via @llvm.ptrmask()
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; intrinsic which is not sufficiently widely-spread yet.
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;
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; https://bugs.llvm.org/show_bug.cgi?id=44448
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; The basic positive tests
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define i32 @t0_32(i32 %ptr, i32 %alignment) nounwind {
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; X86-LABEL: t0_32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: decl %ecx
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; X86-NEXT: andl %eax, %ecx
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; X86-NEXT: subl %ecx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: t0_32:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: decl %esi
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; X64-NEXT: andl %edi, %esi
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; X64-NEXT: subl %esi, %eax
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; X64-NEXT: retq
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%mask = add i32 %alignment, -1
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%bias = and i32 %ptr, %mask
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%r = sub i32 %ptr, %bias
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ret i32 %r
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}
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define i64 @t1_64(i64 %ptr, i64 %alignment) nounwind {
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; X86-LABEL: t1_64:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: addl $-1, %ecx
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; X86-NEXT: adcl $-1, %esi
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; X86-NEXT: andl %edx, %esi
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; X86-NEXT: andl %eax, %ecx
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; X86-NEXT: subl %ecx, %eax
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; X86-NEXT: sbbl %esi, %edx
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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;
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; X64-LABEL: t1_64:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: decq %rsi
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; X64-NEXT: andq %rdi, %rsi
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; X64-NEXT: subq %rsi, %rax
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; X64-NEXT: retq
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%mask = add i64 %alignment, -1
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%bias = and i64 %ptr, %mask
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%r = sub i64 %ptr, %bias
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ret i64 %r
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}
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define i32 @t2_commutative(i32 %ptr, i32 %alignment) nounwind {
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; X86-LABEL: t2_commutative:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: decl %ecx
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; X86-NEXT: andl %eax, %ecx
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; X86-NEXT: subl %ecx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: t2_commutative:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: decl %esi
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; X64-NEXT: andl %edi, %esi
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; X64-NEXT: subl %esi, %eax
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; X64-NEXT: retq
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%mask = add i32 %alignment, -1
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%bias = and i32 %mask, %ptr ; swapped
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%r = sub i32 %ptr, %bias
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ret i32 %r
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}
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; Extra use tests
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define i32 @t3_extrause0(i32 %ptr, i32 %alignment, i32* %mask_storage) nounwind {
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; X86-LABEL: t3_extrause0:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: decl %edx
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; X86-NEXT: movl %edx, (%ecx)
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; X86-NEXT: andl %eax, %edx
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; X86-NEXT: subl %edx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: t3_extrause0:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: decl %esi
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; X64-NEXT: movl %esi, (%rdx)
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; X64-NEXT: andl %edi, %esi
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; X64-NEXT: subl %esi, %eax
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; X64-NEXT: retq
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%mask = add i32 %alignment, -1
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store i32 %mask, i32* %mask_storage
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%bias = and i32 %ptr, %mask
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%r = sub i32 %ptr, %bias
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ret i32 %r
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}
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define i32 @n4_extrause1(i32 %ptr, i32 %alignment, i32* %bias_storage) nounwind {
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; X86-LABEL: n4_extrause1:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: decl %edx
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; X86-NEXT: andl %eax, %edx
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; X86-NEXT: movl %edx, (%ecx)
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; X86-NEXT: subl %edx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: n4_extrause1:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: decl %esi
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; X64-NEXT: andl %edi, %esi
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; X64-NEXT: movl %esi, (%rdx)
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; X64-NEXT: subl %esi, %eax
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; X64-NEXT: retq
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%mask = add i32 %alignment, -1
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%bias = and i32 %ptr, %mask ; has extra uses, can't fold
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store i32 %bias, i32* %bias_storage
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%r = sub i32 %ptr, %bias
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ret i32 %r
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}
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define i32 @n5_extrause2(i32 %ptr, i32 %alignment, i32* %mask_storage, i32* %bias_storage) nounwind {
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; X86-LABEL: n5_extrause2:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: decl %esi
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; X86-NEXT: movl %esi, (%edx)
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; X86-NEXT: andl %eax, %esi
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; X86-NEXT: movl %esi, (%ecx)
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; X86-NEXT: subl %esi, %eax
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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;
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; X64-LABEL: n5_extrause2:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: decl %esi
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; X64-NEXT: movl %esi, (%rdx)
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; X64-NEXT: andl %edi, %esi
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; X64-NEXT: movl %esi, (%rcx)
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; X64-NEXT: subl %esi, %eax
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; X64-NEXT: retq
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%mask = add i32 %alignment, -1
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store i32 %mask, i32* %mask_storage
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%bias = and i32 %ptr, %mask ; has extra uses, can't fold
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store i32 %bias, i32* %bias_storage
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%r = sub i32 %ptr, %bias
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ret i32 %r
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}
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; Negative tests
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define i32 @n6_different_ptrs(i32 %ptr0, i32 %ptr1, i32 %alignment) nounwind {
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; X86-LABEL: n6_different_ptrs:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: decl %ecx
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; X86-NEXT: andl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: subl %ecx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: n6_different_ptrs:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: decl %edx
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; X64-NEXT: andl %esi, %edx
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; X64-NEXT: subl %edx, %eax
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; X64-NEXT: retq
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%mask = add i32 %alignment, -1
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%bias = and i32 %ptr1, %mask ; not %ptr0
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%r = sub i32 %ptr0, %bias ; not %ptr1
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ret i32 %r
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}
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define i32 @n7_different_ptrs_commutative(i32 %ptr0, i32 %ptr1, i32 %alignment) nounwind {
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; X86-LABEL: n7_different_ptrs_commutative:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: decl %ecx
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; X86-NEXT: andl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: subl %ecx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: n7_different_ptrs_commutative:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: decl %edx
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; X64-NEXT: andl %esi, %edx
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; X64-NEXT: subl %edx, %eax
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; X64-NEXT: retq
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%mask = add i32 %alignment, -1
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%bias = and i32 %mask, %ptr1 ; swapped, not %ptr0
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%r = sub i32 %ptr0, %bias ; not %ptr1
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ret i32 %r
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}
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define i32 @n8_not_lowbit_mask(i32 %ptr, i32 %alignment) nounwind {
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; X86-LABEL: n8_not_lowbit_mask:
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; X86: # %bb.0:
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NEXT: incl %ecx
|
||||
; X86-NEXT: andl %eax, %ecx
|
||||
; X86-NEXT: subl %ecx, %eax
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: n8_not_lowbit_mask:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: movl %edi, %eax
|
||||
; X64-NEXT: incl %esi
|
||||
; X64-NEXT: andl %edi, %esi
|
||||
; X64-NEXT: subl %esi, %eax
|
||||
; X64-NEXT: retq
|
||||
%mask = add i32 %alignment, 1 ; not -1
|
||||
%bias = and i32 %ptr, %mask
|
||||
%r = sub i32 %ptr, %bias
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define i32 @n9_sub_is_not_commutative(i32 %ptr, i32 %alignment) nounwind {
|
||||
; X86-LABEL: n9_sub_is_not_commutative:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-NEXT: decl %eax
|
||||
; X86-NEXT: andl %ecx, %eax
|
||||
; X86-NEXT: subl %ecx, %eax
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: n9_sub_is_not_commutative:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: movl %esi, %eax
|
||||
; X64-NEXT: decl %eax
|
||||
; X64-NEXT: andl %edi, %eax
|
||||
; X64-NEXT: subl %edi, %eax
|
||||
; X64-NEXT: retq
|
||||
%mask = add i32 %alignment, -1
|
||||
%bias = and i32 %ptr, %mask
|
||||
%r = sub i32 %bias, %ptr ; wrong order
|
||||
ret i32 %r
|
||||
}
|
||||
Loading…
Reference in New Issue