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[X86][SSE] Moved SplitBinaryOpsAndApply earlier so more methods can use it. NFCI. 

llvm-svn: 324841
This commit is contained in:
Simon Pilgrim 2018-02-11 17:01:43 +00:00
parent aee107f30d
commit c2544c572a
1 changed files with 47 additions and 47 deletions
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94
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -5048,6 +5048,53 @@ static SDValue insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
return insertSubVector(Result, Vec, IdxVal, DAG, dl, 256); return insertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
} }
// Helper for splitting operands of a binary operation to legal target size and
// apply a function on each part.
// Useful for operations that are available on SSE2 in 128-bit, on AVX2 in
// 256-bit and on AVX512BW in 512-bit.
// The argument VT is the type used for deciding if/how to split the operands
// Op0 and Op1. Op0 and Op1 do *not* have to be of type VT.
// The argument Builder is a function that will be applied on each split psrt:
// SDValue Builder(SelectionDAG&G, SDLoc, SDValue, SDValue)
template <typename F>
SDValue SplitBinaryOpsAndApply(SelectionDAG &DAG, const X86Subtarget &Subtarget,
const SDLoc &DL, EVT VT, SDValue Op0,
SDValue Op1, F Builder) {
assert(Subtarget.hasSSE2() && "Target assumed to support at least SSE2");
unsigned NumSubs = 1;
if (Subtarget.useBWIRegs()) {
if (VT.getSizeInBits() > 512) {
NumSubs = VT.getSizeInBits() / 512;
assert((VT.getSizeInBits() % 512) == 0 && "Illegal vector size");
}
} else if (Subtarget.hasAVX2()) {
if (VT.getSizeInBits() > 256) {
NumSubs = VT.getSizeInBits() / 256;
assert((VT.getSizeInBits() % 256) == 0 && "Illegal vector size");
}
} else {
if (VT.getSizeInBits() > 128) {
NumSubs = VT.getSizeInBits() / 128;
assert((VT.getSizeInBits() % 128) == 0 && "Illegal vector size");
}
}
if (NumSubs == 1)
return Builder(DAG, DL, Op0, Op1);
SmallVector<SDValue, 4> Subs;
EVT InVT = Op0.getValueType();
EVT SubVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
InVT.getVectorNumElements() / NumSubs);
for (unsigned i = 0; i != NumSubs; ++i) {
unsigned Idx = i * SubVT.getVectorNumElements();
SDValue LHS = extractSubVector(Op0, Idx, DAG, DL, SubVT.getSizeInBits());
SDValue RHS = extractSubVector(Op1, Idx, DAG, DL, SubVT.getSizeInBits());
Subs.push_back(Builder(DAG, DL, LHS, RHS));
}
return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Subs);
}
// Return true if the instruction zeroes the unused upper part of the // Return true if the instruction zeroes the unused upper part of the
// destination and accepts mask. // destination and accepts mask.
static bool isMaskedZeroUpperBitsvXi1(unsigned int Opcode) { static bool isMaskedZeroUpperBitsvXi1(unsigned int Opcode) {
@ -34235,53 +34282,6 @@ static SDValue combineTruncateWithSat(SDValue In, EVT VT, const SDLoc &DL,
return SDValue(); return SDValue();
} }
// Helper for splitting operands of a binary operation to legal target size and
// apply a function on each part.
// Useful for operations that are available on SSE2 in 128-bit, on AVX2 in
// 256-bit and on AVX512BW in 512-bit.
// The argument VT is the type used for deciding if/how to split the operands
// Op0 and Op1. Op0 and Op1 do *not* have to be of type VT.
// The argument Builder is a function that will be applied on each split psrt:
// SDValue Builder(SelectionDAG&G, SDLoc, SDValue, SDValue)
template <typename F>
SDValue SplitBinaryOpsAndApply(SelectionDAG &DAG, const X86Subtarget &Subtarget,
const SDLoc &DL, EVT VT, SDValue Op0,
SDValue Op1, F Builder) {
assert(Subtarget.hasSSE2() && "Target assumed to support at least SSE2");
unsigned NumSubs = 1;
if (Subtarget.useBWIRegs()) {
if (VT.getSizeInBits() > 512) {
NumSubs = VT.getSizeInBits() / 512;
assert((VT.getSizeInBits() % 512) == 0 && "Illegal vector size");
}
} else if (Subtarget.hasAVX2()) {
if (VT.getSizeInBits() > 256) {
NumSubs = VT.getSizeInBits() / 256;
assert((VT.getSizeInBits() % 256) == 0 && "Illegal vector size");
}
} else {
if (VT.getSizeInBits() > 128) {
NumSubs = VT.getSizeInBits() / 128;
assert((VT.getSizeInBits() % 128) == 0 && "Illegal vector size");
}
}
if (NumSubs == 1)
return Builder(DAG, DL, Op0, Op1);
SmallVector<SDValue, 4> Subs;
EVT InVT = Op0.getValueType();
EVT SubVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
InVT.getVectorNumElements() / NumSubs);
for (unsigned i = 0; i != NumSubs; ++i) {
unsigned Idx = i * SubVT.getVectorNumElements();
SDValue LHS = extractSubVector(Op0, Idx, DAG, DL, SubVT.getSizeInBits());
SDValue RHS = extractSubVector(Op1, Idx, DAG, DL, SubVT.getSizeInBits());
Subs.push_back(Builder(DAG, DL, LHS, RHS));
}
return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Subs);
}
/// This function detects the AVG pattern between vectors of unsigned i8/i16, /// This function detects the AVG pattern between vectors of unsigned i8/i16,
/// which is c = (a + b + 1) / 2, and replace this operation with the efficient /// which is c = (a + b + 1) / 2, and replace this operation with the efficient
/// X86ISD::AVG instruction. /// X86ISD::AVG instruction.