[ARM] GlobalISel: Support G_BR

This boils down to not crashing in reg bank select due to the lack of
register operands on this instruction, and adding some tests. The
instruction selection is already covered by the TableGen'erated code.

llvm-svn: 307904

llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp

@@ -331,6 +331,9 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
                             &ARM::ValueMappings[ARM::DPR3OpsIdx]});
     break;
   }
+  case G_BR:
+    OperandsMapping = getOperandsMapping({nullptr});
+    break;
   default:
     return getInvalidInstructionMapping();
   }

llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir

@@ -45,6 +45,8 @@
   define void @test_select_s32() { ret void }
   define void @test_select_ptr() { ret void }
 
+  define void @test_br() { ret void }
+
   define void @test_soft_fp_double() #0 { ret void }
 
   attributes #0 = { "target-features"="+vfp2,-neonfp" }
@@ -1173,6 +1175,25 @@ body:             |
     ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
+name:            test_br
+# CHECK-LABEL: name: test_br
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+body:             |
+  ; CHECK: bb.0
+  bb.0:
+    successors: %bb.1(0x80000000)
+
+  ; CHECK: bb.1
+  bb.1:
+    successors: %bb.1(0x80000000)
+
+    ; CHECK: B %bb.1
+    G_BR %bb.1
+...
+---
 name:            test_soft_fp_double
 # CHECK-LABEL: name: test_soft_fp_double
 legalized:       true

llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll

@@ -420,3 +420,14 @@ entry:
   %r = select i1 %cond, i32* %a, i32* %b
   ret i32* %r
 }
+
+define arm_aapcscc void @test_br() {
+; CHECK-LABEL: test_br
+; CHECK: [[LABEL:.L[[:alnum:]_]+]]:
+; CHECK: b [[LABEL]]
+entry:
+  br label %infinite
+
+infinite:
+  br label %infinite
+}

llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

@@ -40,6 +40,8 @@
 
   define void @test_select_s32() { ret void }
 
+  define void @test_br() { ret void }
+
   define void @test_fadd_s32() #0 { ret void }
   define void @test_fadd_s64() #0 { ret void }
 
@@ -828,6 +830,24 @@ body:             |
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
 
+...
+---
+name:            test_br
+# CHECK-LABEL: name: test_br
+legalized:       true
+regBankSelected: false
+# CHECK: regBankSelected: true
+# There aren't any registers to map, but make sure we don't crash.
+selected:        false
+body:             |
+  bb.0:
+    successors: %bb.1(0x80000000)
+
+  bb.1:
+    successors: %bb.1(0x80000000)
+
+    G_BR %bb.1
+
 ...
 ---
 name:            test_fadd_s32