[InstCombine] add/adjust tests for add+xor -> shifts; NFC
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Sanjay Patel
parent
86f69689f9
commit
c5138e61e1
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@ -3,62 +3,112 @@
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target datalayout = "n8:16:32:64"
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define i32 @test1(i32 %x) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %x, 16
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; CHECK-NEXT: [[TMP_3:%.*]] = ashr exact i32 [[SEXT]], 16
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; CHECK-NEXT: ret i32 [[TMP_3]]
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define i32 @sextinreg(i32 %x) {
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; CHECK-LABEL: @sextinreg(
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; CHECK-NEXT: [[SEXT:%.*]] = shl i32 [[X:%.*]], 16
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; CHECK-NEXT: [[T3:%.*]] = ashr exact i32 [[SEXT]], 16
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%tmp.1 = and i32 %x, 65535
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%tmp.2 = xor i32 %tmp.1, -32768
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%tmp.3 = add i32 %tmp.2, 32768
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ret i32 %tmp.3
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%t1 = and i32 %x, 65535
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%t2 = xor i32 %t1, -32768
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%t3 = add i32 %t2, 32768
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ret i32 %t3
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}
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define i32 @test2(i32 %x) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %x, 16
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; CHECK-NEXT: [[TMP_3:%.*]] = ashr exact i32 [[SEXT]], 16
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; CHECK-NEXT: ret i32 [[TMP_3]]
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define <2 x i32> @sextinreg_splat(<2 x i32> %x) {
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; CHECK-LABEL: @sextinreg_splat(
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; CHECK-NEXT: [[T1:%.*]] = and <2 x i32> [[X:%.*]], <i32 65535, i32 65535>
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; CHECK-NEXT: [[T2:%.*]] = xor <2 x i32> [[T1]], <i32 -32768, i32 -32768>
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; CHECK-NEXT: [[T3:%.*]] = add nsw <2 x i32> [[T2]], <i32 32768, i32 32768>
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; CHECK-NEXT: ret <2 x i32> [[T3]]
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;
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%tmp.1 = and i32 %x, 65535
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%tmp.2 = xor i32 %tmp.1, 32768
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%tmp.3 = add i32 %tmp.2, -32768
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ret i32 %tmp.3
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%t1 = and <2 x i32> %x, <i32 65535, i32 65535>
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%t2 = xor <2 x i32> %t1, <i32 -32768, i32 -32768>
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%t3 = add <2 x i32> %t2, <i32 32768, i32 32768>
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ret <2 x i32> %t3
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}
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define i32 @test3(i16 %P) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: [[TMP_5:%.*]] = sext i16 %P to i32
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; CHECK-NEXT: ret i32 [[TMP_5]]
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define i32 @sextinreg_alt(i32 %x) {
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; CHECK-LABEL: @sextinreg_alt(
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; CHECK-NEXT: [[SEXT:%.*]] = shl i32 [[X:%.*]], 16
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; CHECK-NEXT: [[T3:%.*]] = ashr exact i32 [[SEXT]], 16
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%tmp.1 = zext i16 %P to i32
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%tmp.4 = xor i32 %tmp.1, 32768
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%tmp.5 = add i32 %tmp.4, -32768
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ret i32 %tmp.5
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%t1 = and i32 %x, 65535
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%t2 = xor i32 %t1, 32768
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%t3 = add i32 %t2, -32768
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ret i32 %t3
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}
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define i32 @test4(i32 %x) {
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; CHECK-LABEL: @test4(
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; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %x, 24
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; CHECK-NEXT: [[TMP_3:%.*]] = ashr exact i32 [[SEXT]], 24
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; CHECK-NEXT: ret i32 [[TMP_3]]
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define <2 x i32> @sextinreg_alt_splat(<2 x i32> %x) {
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; CHECK-LABEL: @sextinreg_alt_splat(
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; CHECK-NEXT: [[T1:%.*]] = and <2 x i32> [[X:%.*]], <i32 65535, i32 65535>
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; CHECK-NEXT: [[T2:%.*]] = xor <2 x i32> [[T1]], <i32 32768, i32 32768>
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; CHECK-NEXT: [[T3:%.*]] = add nsw <2 x i32> [[T2]], <i32 -32768, i32 -32768>
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; CHECK-NEXT: ret <2 x i32> [[T3]]
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;
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%tmp.1 = and i32 %x, 255
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%tmp.2 = xor i32 %tmp.1, 128
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%tmp.3 = add i32 %tmp.2, -128
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ret i32 %tmp.3
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%t1 = and <2 x i32> %x, <i32 65535, i32 65535>
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%t2 = xor <2 x i32> %t1, <i32 32768, i32 32768>
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%t3 = add <2 x i32> %t2, <i32 -32768, i32 -32768>
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ret <2 x i32> %t3
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}
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define i32 @sext(i16 %P) {
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; CHECK-LABEL: @sext(
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; CHECK-NEXT: [[T5:%.*]] = sext i16 [[P:%.*]] to i32
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; CHECK-NEXT: ret i32 [[T5]]
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;
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%t1 = zext i16 %P to i32
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%t4 = xor i32 %t1, 32768
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%t5 = add i32 %t4, -32768
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ret i32 %t5
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}
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define <2 x i32> @sext_splat(<2 x i16> %P) {
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; CHECK-LABEL: @sext_splat(
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; CHECK-NEXT: [[T5:%.*]] = sext <2 x i16> [[P:%.*]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[T5]]
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;
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%t1 = zext <2 x i16> %P to <2 x i32>
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%t4 = xor <2 x i32> %t1, <i32 32768, i32 32768>
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%t5 = add <2 x i32> %t4, <i32 -32768, i32 -32768>
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ret <2 x i32> %t5
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}
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define i32 @sextinreg2(i32 %x) {
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; CHECK-LABEL: @sextinreg2(
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; CHECK-NEXT: [[SEXT:%.*]] = shl i32 [[X:%.*]], 24
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; CHECK-NEXT: [[T3:%.*]] = ashr exact i32 [[SEXT]], 24
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; CHECK-NEXT: ret i32 [[T3]]
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;
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%t1 = and i32 %x, 255
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%t2 = xor i32 %t1, 128
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%t3 = add i32 %t2, -128
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ret i32 %t3
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}
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define <2 x i32> @sextinreg2_splat(<2 x i32> %x) {
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; CHECK-LABEL: @sextinreg2_splat(
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; CHECK-NEXT: [[T1:%.*]] = and <2 x i32> [[X:%.*]], <i32 255, i32 255>
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; CHECK-NEXT: [[T2:%.*]] = xor <2 x i32> [[T1]], <i32 128, i32 128>
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; CHECK-NEXT: [[T3:%.*]] = add nsw <2 x i32> [[T2]], <i32 -128, i32 -128>
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; CHECK-NEXT: ret <2 x i32> [[T3]]
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;
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%t1 = and <2 x i32> %x, <i32 255, i32 255>
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%t2 = xor <2 x i32> %t1, <i32 128, i32 128>
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%t3 = add <2 x i32> %t2, <i32 -128, i32 -128>
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ret <2 x i32> %t3
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}
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define i32 @test5(i32 %x) {
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: [[TMP_2:%.*]] = shl i32 %x, 16
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; CHECK-NEXT: [[TMP_4:%.*]] = ashr exact i32 [[TMP_2]], 16
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; CHECK-NEXT: ret i32 [[TMP_4]]
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; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], 16
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; CHECK-NEXT: [[T4:%.*]] = ashr exact i32 [[T2]], 16
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; CHECK-NEXT: ret i32 [[T4]]
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;
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%tmp.2 = shl i32 %x, 16
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%tmp.4 = ashr i32 %tmp.2, 16
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ret i32 %tmp.4
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%t2 = shl i32 %x, 16
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%t4 = ashr i32 %t2, 16
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ret i32 %t4
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}
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; If the shift amount equals the difference in width of the destination
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@ -67,20 +117,20 @@ define i32 @test5(i32 %x) {
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define i32 @test6(i16 %P) {
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; CHECK-LABEL: @test6(
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; CHECK-NEXT: [[TMP_5:%.*]] = sext i16 %P to i32
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; CHECK-NEXT: ret i32 [[TMP_5]]
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; CHECK-NEXT: [[T5:%.*]] = sext i16 [[P:%.*]] to i32
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; CHECK-NEXT: ret i32 [[T5]]
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;
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%tmp.1 = zext i16 %P to i32
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%sext1 = shl i32 %tmp.1, 16
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%tmp.5 = ashr i32 %sext1, 16
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ret i32 %tmp.5
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%t1 = zext i16 %P to i32
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%sext1 = shl i32 %t1, 16
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%t5 = ashr i32 %sext1, 16
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ret i32 %t5
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}
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; Vectors should get the same fold as above.
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define <2 x i32> @test6_splat_vec(<2 x i12> %P) {
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; CHECK-LABEL: @test6_splat_vec(
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; CHECK-NEXT: [[ASHR:%.*]] = sext <2 x i12> %P to <2 x i32>
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; CHECK-NEXT: [[ASHR:%.*]] = sext <2 x i12> [[P:%.*]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[ASHR]]
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;
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%z = zext <2 x i12> %P to <2 x i32>
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@ -89,9 +139,9 @@ define <2 x i32> @test6_splat_vec(<2 x i12> %P) {
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ret <2 x i32> %ashr
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}
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define i32 @test7(i32 %x) {
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; CHECK-LABEL: @test7(
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; CHECK-NEXT: [[SUB:%.*]] = ashr i32 %x, 5
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define i32 @ashr(i32 %x) {
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; CHECK-LABEL: @ashr(
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; CHECK-NEXT: [[SUB:%.*]] = ashr i32 [[X:%.*]], 5
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; CHECK-NEXT: ret i32 [[SUB]]
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;
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%shr = lshr i32 %x, 5
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@ -100,3 +150,15 @@ define i32 @test7(i32 %x) {
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ret i32 %sub
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}
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define <2 x i32> @ashr_splat(<2 x i32> %x) {
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; CHECK-LABEL: @ashr_splat(
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; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 5, i32 5>
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; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i32> [[SHR]], <i32 67108864, i32 67108864>
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; CHECK-NEXT: [[SUB:%.*]] = add nsw <2 x i32> [[XOR]], <i32 -67108864, i32 -67108864>
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; CHECK-NEXT: ret <2 x i32> [[SUB]]
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;
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%shr = lshr <2 x i32> %x, <i32 5, i32 5>
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%xor = xor <2 x i32> %shr, <i32 67108864, i32 67108864>
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%sub = add <2 x i32> %xor, <i32 -67108864, i32 -67108864>
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ret <2 x i32> %sub
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}
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