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[X86][SSE] Tidyup with implicit SDValue bool check. NFC. 

llvm-svn: 253171
This commit is contained in:
Simon Pilgrim 2015-11-15 14:57:07 +00:00
parent 83d03ddbf6
commit cbba348ae7
1 changed files with 5 additions and 8 deletions
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13
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -11182,7 +11182,7 @@ static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
unsigned &MaskValue) { unsigned &MaskValue) {
MaskValue = 0; MaskValue = 0;
unsigned NumElems = BuildVector->getNumOperands(); unsigned NumElems = BuildVector->getNumOperands();
// There are 2 lanes if (NumElems > 8), and 1 lane otherwise. // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
// We don't handle the >2 lanes case right now. // We don't handle the >2 lanes case right now.
unsigned NumLanes = (NumElems - 1) / 8 + 1; unsigned NumLanes = (NumElems - 1) / 8 + 1;
@ -14524,8 +14524,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
Op1.getOpcode() == ISD::Constant && Op1.getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(Op1)->isNullValue() && cast<ConstantSDNode>(Op1)->isNullValue() &&
(CC == ISD::SETEQ || CC == ISD::SETNE)) { (CC == ISD::SETEQ || CC == ISD::SETNE)) {
SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
if (NewSetCC.getNode()) {
if (VT == MVT::i1) if (VT == MVT::i1)
return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC); return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
return NewSetCC; return NewSetCC;
@ -14846,8 +14845,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
// We know the result of AND is compared against zero. Try to match // We know the result of AND is compared against zero. Try to match
// it to BT. // it to BT.
if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
if (NewSetCC.getNode()) {
CC = NewSetCC.getOperand(0); CC = NewSetCC.getOperand(0);
Cond = NewSetCC.getOperand(1); Cond = NewSetCC.getOperand(1);
addTest = false; addTest = false;
@ -15530,8 +15528,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
// We know the result of AND is compared against zero. Try to match // We know the result of AND is compared against zero. Try to match
// it to BT. // it to BT.
if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) {
if (NewSetCC.getNode()) {
CC = NewSetCC.getOperand(0); CC = NewSetCC.getOperand(0);
Cond = NewSetCC.getOperand(1); Cond = NewSetCC.getOperand(1);
addTest = false; addTest = false;
@ -26518,7 +26515,7 @@ static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
} }
// Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
// a 32-bit target where SSE doesn't support i64->FP operations. // a 32-bit target where SSE doesn't support i64->FP operations.
if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) { if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
EVT LdVT = Ld->getValueType(0); EVT LdVT = Ld->getValueType(0);