diff --git a/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h b/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h index bc923282062a..0b4ea99d06db 100644 --- a/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h +++ b/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h @@ -68,8 +68,8 @@ public: InOrderIssueStage(RetireControlUnit &RCU, RegisterFile &PRF, const MCSchedModel &SM, const MCSubtargetInfo &STI) : SM(SM), STI(STI), RCU(RCU), PRF(PRF), - RM(std::make_unique(SM)), StallCyclesLeft(0), - Bandwidth(0) {} + RM(std::make_unique(SM)), NumIssued(0), + StallCyclesLeft(0), Bandwidth(0) {} bool isAvailable(const InstRef &) const override; bool hasWorkToComplete() const override;