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[AArch64] Consistently separate asm opc and operands with '\t'. 

Some of the instructions use ' ', which drives OCD-me nuts.
Let's put an end to this.

NFC-ish: hopefully nobody cares about whitespace.
llvm-svn: 246686
This commit is contained in:
Ahmed Bougacha 2015-09-02 18:38:36 +00:00
parent 04430aea68
commit cca07716f5
1 changed files with 17 additions and 17 deletions
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34
llvm/lib/Target/AArch64/AArch64InstrFormats.td
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@ -2525,7 +2525,7 @@ class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
} }
class ROInstAlias<string asm, RegisterClass regtype, Instruction INST> class ROInstAlias<string asm, RegisterClass regtype, Instruction INST>
: InstAlias<asm # " $Rt, [$Rn, $Rm]", : InstAlias<asm # "\t$Rt, [$Rn, $Rm]",
(INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>; (INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
@ -2951,7 +2951,7 @@ multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
(ins GPR64sp:$Rn, simm9:$offset), asm, pattern>, (ins GPR64sp:$Rn, simm9:$offset), asm, pattern>,
Sched<[WriteLD]>; Sched<[WriteLD]>;
def : InstAlias<asm # " $Rt, [$Rn]", def : InstAlias<asm # "\t$Rt, [$Rn]",
(!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>; (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
} }
@ -2963,7 +2963,7 @@ multiclass StoreUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
asm, pattern>, asm, pattern>,
Sched<[WriteST]>; Sched<[WriteST]>;
def : InstAlias<asm # " $Rt, [$Rn]", def : InstAlias<asm # "\t$Rt, [$Rn]",
(!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>; (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
} }
@ -2975,7 +2975,7 @@ multiclass PrefetchUnscaled<bits<2> sz, bit V, bits<2> opc, string asm,
asm, pat>, asm, pat>,
Sched<[WriteLD]>; Sched<[WriteLD]>;
def : InstAlias<asm # " $Rt, [$Rn]", def : InstAlias<asm # "\t$Rt, [$Rn]",
(!cast<Instruction>(NAME # "i") prfop:$Rt, GPR64sp:$Rn, 0)>; (!cast<Instruction>(NAME # "i") prfop:$Rt, GPR64sp:$Rn, 0)>;
} }
@ -3010,7 +3010,7 @@ multiclass LoadUnprivileged<bits<2> sz, bit V, bits<2> opc,
(ins GPR64sp:$Rn, simm9:$offset), asm>, (ins GPR64sp:$Rn, simm9:$offset), asm>,
Sched<[WriteLD]>; Sched<[WriteLD]>;
def : InstAlias<asm # " $Rt, [$Rn]", def : InstAlias<asm # "\t$Rt, [$Rn]",
(!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>; (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
} }
@ -3022,7 +3022,7 @@ multiclass StoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
asm>, asm>,
Sched<[WriteST]>; Sched<[WriteST]>;
def : InstAlias<asm # " $Rt, [$Rn]", def : InstAlias<asm # "\t$Rt, [$Rn]",
(!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>; (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
} }
@ -3153,7 +3153,7 @@ multiclass LoadPairOffset<bits<2> opc, bit V, RegisterClass regtype,
(ins GPR64sp:$Rn, indextype:$offset), asm>, (ins GPR64sp:$Rn, indextype:$offset), asm>,
Sched<[WriteLD, WriteLDHi]>; Sched<[WriteLD, WriteLDHi]>;
def : InstAlias<asm # " $Rt, $Rt2, [$Rn]", def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
(!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2, (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
GPR64sp:$Rn, 0)>; GPR64sp:$Rn, 0)>;
} }
@ -3168,7 +3168,7 @@ multiclass StorePairOffset<bits<2> opc, bit V, RegisterClass regtype,
asm>, asm>,
Sched<[WriteSTP]>; Sched<[WriteSTP]>;
def : InstAlias<asm # " $Rt, $Rt2, [$Rn]", def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
(!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2, (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
GPR64sp:$Rn, 0)>; GPR64sp:$Rn, 0)>;
} }
@ -4791,17 +4791,17 @@ multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
asm, ".2d", "0.0", asm, ".2d", "0.0",
v2i64, v2f64, OpNode>; v2i64, v2f64, OpNode>;
def : InstAlias<asm # " $Vd.2s, $Vn.2s, #0", def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0",
(!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>; (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
def : InstAlias<asm # " $Vd.4s, $Vn.4s, #0", def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0",
(!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>; (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
def : InstAlias<asm # " $Vd.2d, $Vn.2d, #0", def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0",
(!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>; (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
def : InstAlias<asm # ".2s $Vd, $Vn, #0", def : InstAlias<asm # ".2s\t$Vd, $Vn, #0",
(!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>; (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
def : InstAlias<asm # ".4s $Vd, $Vn, #0", def : InstAlias<asm # ".4s\t$Vd, $Vn, #0",
(!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>; (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
def : InstAlias<asm # ".2d $Vd, $Vn, #0", def : InstAlias<asm # ".2d\t$Vd, $Vn, #0",
(!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>; (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
} }
@ -5589,9 +5589,9 @@ multiclass SIMDFPCmpTwoScalar<bit U, bit S, bits<5> opc, string asm,
def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, opc, FPR64, asm, "0.0">; def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, opc, FPR64, asm, "0.0">;
def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, opc, FPR32, asm, "0.0">; def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, opc, FPR32, asm, "0.0">;
def : InstAlias<asm # " $Rd, $Rn, #0", def : InstAlias<asm # "\t$Rd, $Rn, #0",
(!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>; (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>;
def : InstAlias<asm # " $Rd, $Rn, #0", def : InstAlias<asm # "\t$Rd, $Rn, #0",
(!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn), 0>; (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn), 0>;
def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))), def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
@ -5947,7 +5947,7 @@ class SIMDInsMainMovAlias<string size, Instruction inst,
class SIMDInsElementMovAlias<string size, Instruction inst, class SIMDInsElementMovAlias<string size, Instruction inst,
Operand idxtype> Operand idxtype>
: InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" # : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" #
# "|" # size #" $dst$idx, $src$idx2}", # "|" # size #"\t$dst$idx, $src$idx2}",
(inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>; (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>;