[AMDGPU] Add wave barrier builtin
The wave barrier represents the discardable barrier. Its main purpose is to carry convergent attribute, thus preventing illegal CFG optimizations. All lanes in a wave come to convergence point simultaneously with SIMT, thus no special instruction is needed in the ISA. The barrier is discarded during code generation. Differential Revision: https://reviews.llvm.org/D26584 llvm-svn: 287006
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@ -36,6 +36,7 @@ BUILTIN(__builtin_amdgcn_workitem_id_z, "Ui", "nc")
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// Instruction builtins.
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//===----------------------------------------------------------------------===//
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BUILTIN(__builtin_amdgcn_s_barrier, "v", "n")
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BUILTIN(__builtin_amdgcn_wave_barrier, "v", "n")
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BUILTIN(__builtin_amdgcn_div_scale, "dddbb*", "n")
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BUILTIN(__builtin_amdgcn_div_scalef, "fffbb*", "n")
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BUILTIN(__builtin_amdgcn_div_fmas, "ddddb", "nc")
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@ -270,6 +270,13 @@ void test_s_barrier()
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__builtin_amdgcn_s_barrier();
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}
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// CHECK-LABEL: @test_wave_barrier
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// CHECK: call void @llvm.amdgcn.wave.barrier(
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void test_wave_barrier()
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{
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__builtin_amdgcn_wave_barrier();
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}
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// CHECK-LABEL: @test_s_memtime
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// CHECK: call i64 @llvm.amdgcn.s.memtime()
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void test_s_memtime(global ulong* out)
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