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added a few 1 operand form stuff. Seems to break regalloc on alpha. sigh 

llvm-svn: 23849
This commit is contained in:
Andrew Lenharth 2005-10-20 19:39:24 +00:00
parent 7e0e8234f6
commit d4c0ed74e4
3 changed files with 33 additions and 13 deletions
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6
llvm/lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -697,7 +697,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
Opc = opcode == ISD::CTPOP ? Alpha::CTPOP : Opc = opcode == ISD::CTPOP ? Alpha::CTPOP :
(opcode == ISD::CTTZ ? Alpha::CTTZ : Alpha::CTLZ); (opcode == ISD::CTTZ ? Alpha::CTTZ : Alpha::CTLZ);
Tmp1 = SelectExpr(N.getOperand(0)); Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Opc, 1, Result).addReg(Alpha::R31).addReg(Tmp1); BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
return Result; return Result;
case ISD::MULHU: case ISD::MULHU:
@ -1084,10 +1084,10 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
break; break;
} }
case MVT::i16: case MVT::i16:
BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Alpha::R31).addReg(Tmp1); BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Tmp1);
break; break;
case MVT::i8: case MVT::i8:
BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Alpha::R31).addReg(Tmp1); BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1);
break; break;
case MVT::i1: case MVT::i1:
Tmp2 = MakeReg(MVT::i64); Tmp2 = MakeReg(MVT::i64);

16
llvm/lib/Target/Alpha/AlphaInstrFormats.td
View File

@ -110,6 +110,22 @@ class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
let Inst{4-0} = Rc; let Inst{4-0} = Rc;
} }
class OFormT<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern>
: InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RB), asmstr> {
let Pattern = pattern;
bits<5> Rc;
bits<5> Rb;
bits<7> Function = fun;
let Inst{25-21} = 0;
let Inst{20-16} = Rb;
let Inst{15-13} = 0;
let Inst{12} = 0;
let Inst{11-5} = Function;
let Inst{4-0} = Rc;
}
class OcmForm<bits<6> opcode, bits<7> fun, dag OL, string asmstr> class OcmForm<bits<6> opcode, bits<7> fun, dag OL, string asmstr>
: InstAlpha<opcode, OL, asmstr> { : InstAlpha<opcode, OL, asmstr> {
bits<5> Ra; bits<5> Ra;

24
llvm/lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -145,10 +145,12 @@ def BIS : OForm< 0x11, 0x20, "bis $RA,$RB,$RC",
[(set GPRC:$RC, (or GPRC:$RA, GPRC:$RB))]>; [(set GPRC:$RC, (or GPRC:$RA, GPRC:$RB))]>;
def BISi : OFormL<0x11, 0x20, "bis $RA,$L,$RC", def BISi : OFormL<0x11, 0x20, "bis $RA,$L,$RC",
[(set GPRC:$RC, (or GPRC:$RA, immUExt8:$L))]>; [(set GPRC:$RC, (or GPRC:$RA, immUExt8:$L))]>;
def CTLZ : OForm< 0x1C, 0x32, "CTLZ $RB,$RC", []>; def CTLZ : OFormT<0x1C, 0x32, "CTLZ $RB,$RC",
// [(set GPRC:$RC, (ctlz GPRC:$RB))]>; [(set GPRC:$RC, (ctlz GPRC:$RB))]>;
def CTPOP : OForm< 0x1C, 0x30, "CTPOP $RB,$RC", []>; //Count population def CTPOP : OFormT<0x1C, 0x30, "CTPOP $RB,$RC",
def CTTZ : OForm< 0x1C, 0x33, "CTTZ $RB,$RC", []>; //Count trailing zero [(set GPRC:$RC, (ctpop GPRC:$RB))]>;
def CTTZ : OFormT<0x1C, 0x33, "CTTZ $RB,$RC",
[(set GPRC:$RC, (cttz GPRC:$RB))]>;
def EQV : OForm< 0x11, 0x48, "eqv $RA,$RB,$RC", def EQV : OForm< 0x11, 0x48, "eqv $RA,$RB,$RC",
[(set GPRC:$RC, (xor GPRC:$RA, (not GPRC:$RB)))]>; [(set GPRC:$RC, (xor GPRC:$RA, (not GPRC:$RB)))]>;
def EQVi : OFormL<0x11, 0x48, "eqv $RA,$L,$RC", []>; def EQVi : OFormL<0x11, 0x48, "eqv $RA,$L,$RC", []>;
@ -252,10 +254,10 @@ def S8SUBQ : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC",
[(set GPRC:$RC, (sub8 GPRC:$RA, GPRC:$RB))]>; [(set GPRC:$RC, (sub8 GPRC:$RA, GPRC:$RB))]>;
def S8SUBQi : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC", def S8SUBQi : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC",
[(set GPRC:$RC, (sub8 GPRC:$RA, immUExt8:$L))]>; [(set GPRC:$RC, (sub8 GPRC:$RA, immUExt8:$L))]>;
def SEXTB : OFormT<0x1C, 0x00, "sextb $RB,$RC",
def SEXTB : OForm< 0x1C, 0x00, "sextb $RB,$RC", []>; //Sign extend byte [(set GPRC:$RC, (sext_inreg GPRC:$RB, i8))]>;
def SEXTW : OForm< 0x1C, 0x01, "sextw $RB,$RC", []>; //Sign extend word def SEXTW : OFormT<0x1C, 0x01, "sextw $RB,$RC",
[(set GPRC:$RC, (sext_inreg GPRC:$RB, i16))]>;
def SL : OForm< 0x12, 0x39, "sll $RA,$RB,$RC", def SL : OForm< 0x12, 0x39, "sll $RA,$RB,$RC",
[(set GPRC:$RC, (shl GPRC:$RA, GPRC:$RB))]>; [(set GPRC:$RC, (shl GPRC:$RA, GPRC:$RB))]>;
def SLi : OFormL<0x12, 0x39, "sll $RA,$L,$RC", def SLi : OFormL<0x12, 0x39, "sll $RA,$L,$RC",
@ -276,8 +278,10 @@ def SUBQ : OForm< 0x10, 0x29, "subq $RA,$RB,$RC",
[(set GPRC:$RC, (sub GPRC:$RA, GPRC:$RB))]>; [(set GPRC:$RC, (sub GPRC:$RA, GPRC:$RB))]>;
def SUBQi : OFormL<0x10, 0x29, "subq $RA,$L,$RC", def SUBQi : OFormL<0x10, 0x29, "subq $RA,$L,$RC",
[(set GPRC:$RC, (sub GPRC:$RA, immUExt8:$L))]>; [(set GPRC:$RC, (sub GPRC:$RA, immUExt8:$L))]>;
def UMULH : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC", []>; //Unsigned multiply quadword high def UMULH : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC",
def UMULHi : OFormL<0x13, 0x30, "umulh $RA,$L,$RC", []>; //Unsigned multiply quadword high [(set GPRC:$RC, (mulhu GPRC:$RA, GPRC:$RB))]>;
def UMULHi : OFormL<0x13, 0x30, "umulh $RA,$L,$RC",
[(set GPRC:$RC, (mulhu GPRC:$RA, immUExt8:$L))]>;
def XOR : OForm< 0x11, 0x40, "xor $RA,$RB,$RC", def XOR : OForm< 0x11, 0x40, "xor $RA,$RB,$RC",
[(set GPRC:$RC, (xor GPRC:$RA, GPRC:$RB))]>; [(set GPRC:$RC, (xor GPRC:$RA, GPRC:$RB))]>;
def XORi : OFormL<0x11, 0x40, "xor $RA,$L,$RC", def XORi : OFormL<0x11, 0x40, "xor $RA,$L,$RC",