AMDGPU/GlobalISel: Remove some problematic testcases
These testcases are a bit nonsensical and won't be handled correctly for a long time. Remove them to unblock load/store legalization work.
This commit is contained in:
Matt Arsenault
parent
7aef99351a
commit
d6270125fc
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@ -1072,154 +1072,3 @@ body: |
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G_STORE %2, %0 :: (store (<3 x s4>), addrspace 1, align 2)
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...
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---
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name: test_truncstore_global_v4s8_to_v4s5_align1
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
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; SI-LABEL: name: test_truncstore_global_v4s8_to_v4s5_align1
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; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; SI: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
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; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
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; SI: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s32)
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; SI: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
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; SI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
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; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
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; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
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; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
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; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
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; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
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; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY2]](s32)
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; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
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; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]]
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; SI: [[COPY4:%[0-9]+]]:_(s16) = COPY [[OR]](s16)
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; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY4]](s16)
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; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[C1]](s32)
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; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY4]](s16)
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; SI: G_STORE [[ANYEXT]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
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; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
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; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
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; SI: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
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; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
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; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
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; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
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; SI: G_STORE [[COPY6]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
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; VI-LABEL: name: test_truncstore_global_v4s8_to_v4s5_align1
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; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; VI: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
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; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
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; VI: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s32)
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; VI: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
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; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
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; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
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; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
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; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
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; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
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; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
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; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
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; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
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; VI: [[COPY2:%[0-9]+]]:_(s16) = COPY [[OR]](s16)
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; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[COPY2]], [[C1]](s16)
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; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY2]](s16)
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; VI: G_STORE [[ANYEXT]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
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; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
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; VI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
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; VI: G_STORE [[ANYEXT1]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
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; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
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; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
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; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
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; VI: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
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%2:_(<4 x s8>) = G_TRUNC %1
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G_STORE %2, %0 :: (store (<4 x s5>), addrspace 1, align 1)
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...
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---
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name: test_truncstore_global_v4s8_to_v4s5_align2
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
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; SI-LABEL: name: test_truncstore_global_v4s8_to_v4s5_align2
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; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; SI: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
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; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
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; SI: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s32)
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; SI: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
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; SI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
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; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
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; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
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; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
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; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
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; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
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; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
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; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]]
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; SI: [[COPY3:%[0-9]+]]:_(s16) = COPY [[OR]](s16)
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; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY3]](s16)
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; SI: G_STORE [[ANYEXT]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
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; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
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; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
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; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
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; SI: G_STORE [[COPY4]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
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; VI-LABEL: name: test_truncstore_global_v4s8_to_v4s5_align2
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; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; VI: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
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; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
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; VI: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV2]](s32)
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; VI: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
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; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
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; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
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; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
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; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV1]](s32)
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; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
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; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
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; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
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; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
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; VI: [[COPY2:%[0-9]+]]:_(s16) = COPY [[OR]](s16)
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; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY2]](s16)
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; VI: G_STORE [[ANYEXT]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
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; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
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; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
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; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
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; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
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%2:_(<4 x s8>) = G_TRUNC %1
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G_STORE %2, %0 :: (store (<4 x s5>), addrspace 1, align 2)
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...
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---
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name: test_truncstore_global_v4s8_to_v4s5_align4
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4_vgpr5
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; SI-LABEL: name: test_truncstore_global_v4s8_to_v4s5_align4
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; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; SI: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
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; SI: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[COPY1]](<4 x s32>)
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; SI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC]](<4 x s8>)
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; SI: G_STORE [[BITCAST]](s32), [[COPY]](p1) :: (store (<4 x s5>), align 4, addrspace 1)
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; VI-LABEL: name: test_truncstore_global_v4s8_to_v4s5_align4
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; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
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; VI: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
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; VI: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[COPY1]](<4 x s32>)
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; VI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC]](<4 x s8>)
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; VI: G_STORE [[BITCAST]](s32), [[COPY]](p1) :: (store (<4 x s5>), align 4, addrspace 1)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
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%2:_(<4 x s8>) = G_TRUNC %1
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G_STORE %2, %0 :: (store (<4 x s5>), addrspace 1, align 4)
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...
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