[ARM][LowOverheadLoops] DoubleWidthResult instructions canGenerateZeros
Given that some instructions generate wider result elements than their inputs, flag them as being able to generate non zeros in the false lanes. Differential Revision: https://reviews.llvm.org/D76766
This commit is contained in:
Sam Parker
parent
ee27df5552
commit
d7084fa34a
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@ -520,27 +520,6 @@ static bool isRegInClass(const MachineOperand &MO,
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return MO.isReg() && MO.getReg() && Class->contains(MO.getReg());
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}
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// Can this instruction generate a non-zero result when given only zeroed
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// operands? This allows us to know that, given operands with false bytes
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// zeroed by masked loads, that the result will also contain zeros in those
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// bytes.
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static bool canGenerateNonZeros(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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default:
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break;
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// FIXME: FP minus 0?
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//case ARM::MVE_VNEGf16:
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//case ARM::MVE_VNEGf32:
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case ARM::MVE_VMVN:
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case ARM::MVE_VORN:
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case ARM::MVE_VCLZs8:
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case ARM::MVE_VCLZs16:
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case ARM::MVE_VCLZs32:
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return true;
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}
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return false;
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}
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// MVE 'narrowing' operate on half a lane, reading from half and writing
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// to half, which are referred to has the top and bottom half. The other
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// half retains its previous value.
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@ -550,6 +529,44 @@ static bool retainsPreviousHalfElement(const MachineInstr &MI) {
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return (Flags & ARMII::RetainsPreviousHalfElement) != 0;
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}
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// Some MVE instructions read from the top/bottom halves of their operand(s)
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// and generate a vector result with result elements that are double the
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// width of the input.
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static bool producesDoubleWidthResult(const MachineInstr &MI) {
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const MCInstrDesc &MCID = MI.getDesc();
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uint64_t Flags = MCID.TSFlags;
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return (Flags & ARMII::DoubleWidthResult) != 0;
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}
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// Can this instruction generate a non-zero result when given only zeroed
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// operands? This allows us to know that, given operands with false bytes
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// zeroed by masked loads, that the result will also contain zeros in those
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// bytes.
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static bool canGenerateNonZeros(const MachineInstr &MI) {
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// Check for instructions which can write into a larger element size,
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// possibly writing into a previous zero'd lane.
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if (producesDoubleWidthResult(MI))
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return true;
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switch (MI.getOpcode()) {
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default:
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break;
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// FIXME: VNEG FP and -0? I think we'll need to handle this once we allow
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// fp16 -> fp32 vector conversions.
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// Instructions that perform a NOT will generate 1s from 0s.
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case ARM::MVE_VMVN:
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case ARM::MVE_VORN:
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// Count leading zeros will do just that!
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case ARM::MVE_VCLZs8:
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case ARM::MVE_VCLZs16:
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case ARM::MVE_VCLZs32:
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return true;
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}
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return false;
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}
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// Look at its register uses to see if it only can only receive zeros
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// into its false lanes which would then produce zeros. Also check that
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// the output register is also defined by an FalseLaneZeros instruction
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@ -751,6 +751,47 @@
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ret i32 %res
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}
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define hidden i32 @illegal_vmull_non_zero(i16* %x, i16* %y, i16* %z, i32 %n) {
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entry:
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%cmp22 = icmp sgt i32 %n, 0
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%0 = add i32 %n, 7
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%1 = icmp slt i32 %n, 8
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%smin = select i1 %1, i32 %n, i32 8
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%2 = sub i32 %0, %smin
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%3 = lshr i32 %2, 3
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%4 = add nuw nsw i32 %3, 1
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br i1 %cmp22, label %while.body.preheader, label %while.end
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while.body.preheader: ; preds = %entry
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call void @llvm.set.loop.iterations.i32(i32 %4)
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br label %while.body
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while.body: ; preds = %while.body.preheader, %while.body
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%x.addr.026 = phi i16* [ %add.ptr, %while.body ], [ %x, %while.body.preheader ]
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%y.addr.025 = phi i16* [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ]
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%n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ]
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%acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ]
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%5 = phi i32 [ %4, %while.body.preheader ], [ %6, %while.body ]
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%tmp3 = bitcast i16* %y.addr.025 to <8 x i16>*
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%tmp1 = bitcast i16* %x.addr.026 to <8 x i16>*
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%tmp = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %n.addr.023)
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%tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)
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%tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)
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%mul = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 1)
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%reduce = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %mul)
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%acc.next = add i32 %reduce, %acc
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%add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 8
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%add.ptr4 = getelementptr inbounds i16, i16* %y.addr.025, i32 8
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%sub = add nsw i32 %n.addr.023, -8
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%6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)
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%7 = icmp ne i32 %6, 0
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br i1 %7, label %while.body, label %while.end
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while.end: ; preds = %while.body, %entry
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%res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ]
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ret i32 %res
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}
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declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32 immarg, <8 x i1>, <8 x i8>)
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declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
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declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>)
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@ -3009,3 +3050,129 @@ body: |
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tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
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...
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---
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name: illegal_vmull_non_zero
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alignment: 2
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tracksRegLiveness: true
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r3', virtual-reg: '' }
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frameInfo:
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: illegal_vmull_non_zero
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000)
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; CHECK: liveins: $lr, $r0, $r1, $r3, $r7
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; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK: tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: $r2 = tMOVr $r3, 14 /* CC::al */, $noreg
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; CHECK: t2IT 10, 8, implicit-def $itstate
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; CHECK: renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate
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; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr
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; CHECK: bb.1.while.body.preheader:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $r0, $r1, $r2, $r3
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; CHECK: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg
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; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
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; CHECK: dead $lr = t2DLS renamable $r2
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; CHECK: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg
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; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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; CHECK: bb.2.while.body:
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; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
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; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg
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; CHECK: MVE_VPST 4, implicit $vpr
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; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2)
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; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2)
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; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg
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; CHECK: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
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; CHECK: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
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; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg
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; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
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; CHECK: bb.3.while.end:
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; CHECK: liveins: $r2
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; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
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; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
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; CHECK: bb.4:
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; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
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; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
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bb.0.entry:
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successors: %bb.1(0x50000000), %bb.4(0x30000000)
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liveins: $r0, $r1, $r3, $r7, $lr
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frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr
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$r2 = tMOVr $r3, 14 /* CC::al */, $noreg
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t2IT 10, 8, implicit-def $itstate
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renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate
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tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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tBcc %bb.4, 11 /* CC::lt */, killed $cpsr
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bb.1.while.body.preheader:
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successors: %bb.2(0x80000000)
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liveins: $r0, $r1, $r2, $r3
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renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg
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renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg
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renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
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t2DoLoopStart renamable $r2
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$r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg
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renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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bb.2.while.body:
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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liveins: $r0, $r1, $r2, $r3, $r12
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renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg
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MVE_VPST 4, implicit $vpr
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renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2)
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renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2)
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$lr = tMOVr $r12, 14 /* CC::al */, $noreg
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renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
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renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
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renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
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renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg
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renamable $lr = t2LoopDec killed renamable $lr, 1
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t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
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tB %bb.3, 14 /* CC::al */, $noreg
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bb.3.while.end:
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liveins: $r2
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$r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
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frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
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bb.4:
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renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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$r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
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frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
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...
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