[AArch64] Add the scheduling model for Exynos-M1
Summary: Add the core scheduling model for the Samsung Exynos-M1 (ARMv8-A). Reviewers: jmolloy, rengolin, christof, MinSeongKIM, t.p.northover Subscribers: aemerson, rengolin, MatzeB Differential Revision: http://reviews.llvm.org/D16644 llvm-svn: 259958
This commit is contained in:
Evandro Menezes
parent
86d7d83f2a
commit
d761ca2308
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@ -90,6 +90,7 @@ def AArch64InstrInfo : InstrInfo;
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include "AArch64SchedA53.td"
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include "AArch64SchedA57.td"
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include "AArch64SchedCyclone.td"
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include "AArch64SchedM1.td"
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def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
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"Cortex-A35 ARM processors",
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@ -144,8 +145,7 @@ def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
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// FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
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def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
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def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
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// FIXME: Exynos-M1 is currently modelled without a specific SchedModel.
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def : ProcessorModel<"exynos-m1", NoSchedModel, [ProcExynosM1]>;
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def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
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//===----------------------------------------------------------------------===//
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// Assembly parser
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@ -0,0 +1,359 @@
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//=- AArch64SchedM1.td - Samsung Exynos-M1 Scheduling Defs ---*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the machine model for Samsung Exynos-M1 to support
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// instruction scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// The Exynos-M1 is a traditional superscalar microprocessor with a
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// 4-wide in-order stage for decode and dispatch and a wider issue stage.
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// The execution units and loads and stores are out-of-order.
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def ExynosM1Model : SchedMachineModel {
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let IssueWidth = 4; // Up to 4 uops per cycle.
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let MinLatency = 0; // OoO.
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let MicroOpBufferSize = 96; // ROB size.
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let LoopMicroOpBufferSize = 32; // Instruction queue size.
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let LoadLatency = 4; // Optimistic load cases.
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let MispredictPenalty = 14; // Minimum branch misprediction penalty.
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let CompleteModel = 0; // Use the default model otherwise.
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}
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//===----------------------------------------------------------------------===//
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// Define each kind of processor resource and number available on the Exynos-M1,
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// which has 9 pipelines, each with its own queue with out-of-order dispatch.
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def M1UnitA : ProcResource<2>; // Simple integer
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def M1UnitC : ProcResource<1>; // Simple and complex integer
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def M1UnitB : ProcResource<2>; // Branch
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def M1UnitL : ProcResource<1>; // Load
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def M1UnitS : ProcResource<1>; // Store
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def M1PipeF0 : ProcResource<1>; // FP #0
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def M1PipeF1 : ProcResource<1>; // FP #1
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let Super = M1PipeF0 in {
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def M1UnitFMAC : ProcResource<1>; // FP multiplication
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def M1UnitFCVT : ProcResource<1>; // FP conversion
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def M1UnitNAL0 : ProcResource<1>; // Simple vector.
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def M1UnitNMISC : ProcResource<1>; // Miscellanea
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def M1UnitNCRYPT : ProcResource<1>; // Cryptographic
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}
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let Super = M1PipeF1 in {
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def M1UnitFADD : ProcResource<1>; // Simple FP
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let BufferSize = 1 in
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def M1UnitFVAR : ProcResource<1>; // FP division & square root (serialized)
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def M1UnitNAL1 : ProcResource<1>; // Simple vector.
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def M1UnitFST : ProcResource<1>; // FP store
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}
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let SchedModel = ExynosM1Model in {
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def M1UnitALU : ProcResGroup<[M1UnitA,
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M1UnitC]>; // All simple integer.
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def M1UnitNALU : ProcResGroup<[M1UnitNAL0,
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M1UnitNAL1]>; // All simple vector.
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}
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let SchedModel = ExynosM1Model in {
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//===----------------------------------------------------------------------===//
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// Coarse scheduling model for the Exynos-M1.
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// Branch instructions.
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// TODO: Non-conditional direct branches take zero cycles and units.
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def : WriteRes<WriteBr, [M1UnitB]> { let Latency = 1; }
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def : WriteRes<WriteBrReg, [M1UnitC]> { let Latency = 1; }
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// TODO: Branch and link is much different.
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// Arithmetic and logical integer instructions.
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def : WriteRes<WriteI, [M1UnitALU]> { let Latency = 1; }
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// TODO: Shift over 3 and some extensions take 2 cycles.
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def : WriteRes<WriteISReg, [M1UnitALU]> { let Latency = 1; }
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def : WriteRes<WriteIEReg, [M1UnitALU]> { let Latency = 1; }
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def : WriteRes<WriteIS, [M1UnitALU]> { let Latency = 1; }
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// Move instructions.
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def : WriteRes<WriteImm, [M1UnitALU]> { let Latency = 1; }
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// Divide and multiply instructions.
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// TODO: Division blocks the divider inside C.
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def : WriteRes<WriteID32, [M1UnitC]> { let Latency = 13; }
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def : WriteRes<WriteID64, [M1UnitC]> { let Latency = 21; }
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// TODO: Long multiplication take 5 cycles and also the ALU.
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// TODO: Multiplication with accumulation can be advanced.
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def : WriteRes<WriteIM32, [M1UnitC]> { let Latency = 3; }
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// TODO: 64-bit multiplication has a throughput of 1/2.
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def : WriteRes<WriteIM64, [M1UnitC]> { let Latency = 4; }
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// Miscellaneous instructions.
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def : WriteRes<WriteExtr, [M1UnitALU,
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M1UnitALU]> { let Latency = 2; }
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// TODO: The latency for the post or pre register is 1 cycle.
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def : WriteRes<WriteAdr, []> { let Latency = 0; }
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// Load instructions.
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def : WriteRes<WriteLD, [M1UnitL]> { let Latency = 4; }
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// TODO: Extended address requires also the ALU.
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def : WriteRes<WriteLDIdx, [M1UnitL]> { let Latency = 5; }
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def : WriteRes<WriteLDHi, [M1UnitALU]> { let Latency = 4; }
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// Store instructions.
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def : WriteRes<WriteST, [M1UnitS]> { let Latency = 1; }
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// TODO: Extended address requires also the ALU.
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def : WriteRes<WriteSTIdx, [M1UnitS]> { let Latency = 1; }
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def : WriteRes<WriteSTP, [M1UnitS]> { let Latency = 1; }
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def : WriteRes<WriteSTX, [M1UnitS]> { let Latency = 1; }
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// FP data instructions.
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def : WriteRes<WriteF, [M1UnitFADD]> { let Latency = 3; }
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// TODO: FCCMP is much different.
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def : WriteRes<WriteFCmp, [M1UnitNMISC]> { let Latency = 4; }
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// TODO: DP takes longer.
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def : WriteRes<WriteFDiv, [M1UnitFVAR]> { let Latency = 15; }
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// TODO: MACC takes longer.
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def : WriteRes<WriteFMul, [M1UnitFMAC]> { let Latency = 4; }
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// FP miscellaneous instructions.
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// TODO: Conversion between register files is much different.
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def : WriteRes<WriteFCvt, [M1UnitFCVT]> { let Latency = 3; }
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def : WriteRes<WriteFImm, [M1UnitNALU]> { let Latency = 1; }
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// TODO: Copy from FPR to GPR is much different.
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def : WriteRes<WriteFCopy, [M1UnitS]> { let Latency = 4; }
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// FP load instructions.
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// TODO: ASIMD loads are much different.
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def : WriteRes<WriteVLD, [M1UnitL]> { let Latency = 5; }
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// FP store instructions.
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// TODO: ASIMD stores are much different.
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def : WriteRes<WriteVST, [M1UnitS, M1UnitFST]> { let Latency = 1; }
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// ASIMD FP instructions.
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// TODO: Other operations are much different.
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def : WriteRes<WriteV, [M1UnitFADD]> { let Latency = 3; }
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// Other miscellaneous instructions.
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def : WriteRes<WriteSys, []> { let Latency = 1; }
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def : WriteRes<WriteBarrier, []> { let Latency = 1; }
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def : WriteRes<WriteHint, []> { let Latency = 1; }
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//===----------------------------------------------------------------------===//
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// Fast forwarding.
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// TODO: Add FP register forwarding rules.
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def : ReadAdvance<ReadI, 0>;
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def : ReadAdvance<ReadISReg, 0>;
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def : ReadAdvance<ReadIEReg, 0>;
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def : ReadAdvance<ReadIM, 0>;
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// Integer multiply-accumulate.
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// TODO: The forwarding for WriteIM64 saves actually 3 cycles.
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def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
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def : ReadAdvance<ReadID, 0>;
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def : ReadAdvance<ReadExtrHi, 0>;
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def : ReadAdvance<ReadAdrBase, 0>;
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def : ReadAdvance<ReadVLD, 0>;
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//===----------------------------------------------------------------------===//
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// Finer scheduling model for the Exynos-M1.
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def M1WriteNEONA : SchedWriteRes<[M1UnitNALU,
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M1UnitNALU,
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M1UnitFADD]> { let Latency = 9; }
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def M1WriteNEONB : SchedWriteRes<[M1UnitNALU,
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M1UnitFST]> { let Latency = 5; }
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def M1WriteNEONC : SchedWriteRes<[M1UnitNALU,
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M1UnitFST]> { let Latency = 6; }
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def M1WriteNEOND : SchedWriteRes<[M1UnitNALU,
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M1UnitFST,
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M1UnitL]> { let Latency = 10; }
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def M1WriteNEONE : SchedWriteRes<[M1UnitFCVT,
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M1UnitFST]> { let Latency = 8; }
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def M1WriteNEONF : SchedWriteRes<[M1UnitFCVT,
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M1UnitFST,
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M1UnitL]> { let Latency = 13; }
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def M1WriteNEONG : SchedWriteRes<[M1UnitNMISC,
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M1UnitFST]> { let Latency = 6; }
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def M1WriteNEONH : SchedWriteRes<[M1UnitNALU,
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M1UnitFST]> { let Latency = 3; }
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def M1WriteNEONI : SchedWriteRes<[M1UnitFST,
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M1UnitL]> { let Latency = 9; }
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def M1WriteALU1 : SchedWriteRes<[M1UnitALU]> { let Latency = 1; }
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def M1WriteB : SchedWriteRes<[M1UnitB]> { let Latency = 1; }
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// FIXME: This is the worst case, conditional branch and link.
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def M1WriteBL : SchedWriteRes<[M1UnitB,
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M1UnitALU]> { let Latency = 1; }
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// FIXME: This is the worst case, when using LR.
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def M1WriteBLR : SchedWriteRes<[M1UnitB,
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M1UnitALU,
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M1UnitALU]> { let Latency = 2; }
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def M1WriteC1 : SchedWriteRes<[M1UnitC]> { let Latency = 1; }
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def M1WriteC2 : SchedWriteRes<[M1UnitC]> { let Latency = 2; }
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def M1WriteFADD3 : SchedWriteRes<[M1UnitFADD]> { let Latency = 3; }
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def M1WriteFCVT3 : SchedWriteRes<[M1UnitFCVT]> { let Latency = 3; }
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def M1WriteFCVT4 : SchedWriteRes<[M1UnitFCVT]> { let Latency = 4; }
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def M1WriteFMAC4 : SchedWriteRes<[M1UnitFMAC]> { let Latency = 4; }
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def M1WriteFMAC5 : SchedWriteRes<[M1UnitFMAC]> { let Latency = 5; }
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def M1WriteFVAR15 : SchedWriteRes<[M1UnitFVAR]> { let Latency = 15; }
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def M1WriteFVAR23 : SchedWriteRes<[M1UnitFVAR]> { let Latency = 23; }
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def M1WriteNALU1 : SchedWriteRes<[M1UnitNALU]> { let Latency = 1; }
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def M1WriteNALU2 : SchedWriteRes<[M1UnitNALU]> { let Latency = 2; }
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def M1WriteNAL11 : SchedWriteRes<[M1UnitNAL1]> { let Latency = 1; }
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def M1WriteNAL12 : SchedWriteRes<[M1UnitNAL1]> { let Latency = 2; }
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def M1WriteNAL13 : SchedWriteRes<[M1UnitNAL1]> { let Latency = 3; }
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def M1WriteNCRYPT1 : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 1; }
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def M1WriteNCRYPT5 : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 5; }
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def M1WriteNMISC1 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 1; }
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def M1WriteNMISC2 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 2; }
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def M1WriteNMISC3 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 3; }
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def M1WriteNMISC4 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 4; }
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def M1WriteS4 : SchedWriteRes<[M1UnitS]> { let Latency = 4; }
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def M1WriteTB : SchedWriteRes<[M1UnitC,
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M1UnitALU]> { let Latency = 2; }
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// Branch instructions
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def : InstRW<[M1WriteB ], (instrs Bcc)>;
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def : InstRW<[M1WriteBL], (instrs BL)>;
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def : InstRW<[M1WriteBLR], (instrs BLR)>;
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def : InstRW<[M1WriteC1], (instregex "^CBN?Z[WX]")>;
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def : InstRW<[M1WriteTB], (instregex "^TBN?Z[WX]")>;
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// Arithmetic and logical integer instructions.
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def : InstRW<[M1WriteALU1], (instrs COPY)>;
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// Divide and multiply instructions.
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// Miscellaneous instructions.
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// Load instructions.
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// Store instructions.
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// FP data instructions.
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def : InstRW<[M1WriteNALU1], (instregex "^F(ABS|NEG)[DS]r")>;
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def : InstRW<[M1WriteFADD3], (instregex "^F(ADD|SUB)[DS]rr")>;
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def : InstRW<[M1WriteNEONG], (instregex "^FCCMPE?[DS]rr")>;
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def : InstRW<[M1WriteNMISC4], (instregex "^FCMPE?[DS]r")>;
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def : InstRW<[M1WriteFVAR15], (instrs FDIVSrr)>;
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def : InstRW<[M1WriteFVAR23], (instrs FDIVDrr)>;
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def : InstRW<[M1WriteNMISC2], (instregex "^F(MAX|MIN).+rr")>;
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def : InstRW<[M1WriteFMAC4], (instregex "^FN?MUL[DS]rr")>;
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def : InstRW<[M1WriteFMAC5], (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
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def : InstRW<[M1WriteFCVT3], (instregex "^FRINT.+r")>;
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def : InstRW<[M1WriteNEONH], (instregex "^FCSEL[DS]rrr")>;
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def : InstRW<[M1WriteFVAR15], (instrs FSQRTSr)>;
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def : InstRW<[M1WriteFVAR23], (instrs FSQRTDr)>;
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// FP miscellaneous instructions.
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def : InstRW<[M1WriteFCVT3], (instregex "^FCVT[DS][DS]r")>;
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def : InstRW<[M1WriteNEONF], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>;
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def : InstRW<[M1WriteNEONE], (instregex "^[SU]CVTF[SU]")>;
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def : InstRW<[M1WriteNALU1], (instregex "^FMOV[DS][ir]")>;
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def : InstRW<[M1WriteS4], (instregex "^FMOV[WX][DS](High)?r")>;
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def : InstRW<[M1WriteNEONI], (instregex "^FMOV[DS][WX](High)?r")>;
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// FP load instructions.
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// FP store instructions.
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// ASIMD instructions.
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def : InstRW<[M1WriteNMISC3], (instregex "^[SU]ABAL?v")>;
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def : InstRW<[M1WriteNMISC1], (instregex "^[SU]ABDL?v")>;
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def : InstRW<[M1WriteNMISC1], (instregex "^(SQ)?ABSv")>;
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def : InstRW<[M1WriteNMISC1], (instregex "^SQNEGv")>;
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def : InstRW<[M1WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>;
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def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?H(ADD|SUB)v")>;
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def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?AD[AD](L|LP|P|W)V?2?v")>;
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def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?SUB[LW]2?v")>;
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def : InstRW<[M1WriteNMISC3], (instregex "^R?(ADD|SUB)HN?2?v")>;
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def : InstRW<[M1WriteNMISC3], (instregex "^[SU]+Q(ADD|SUB)v")>;
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def : InstRW<[M1WriteNMISC3], (instregex "^[SU]RHADDv")>;
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def : InstRW<[M1WriteNMISC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
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def : InstRW<[M1WriteNALU1], (instregex "^CMTSTv")>;
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def : InstRW<[M1WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
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def : InstRW<[M1WriteNMISC1], (instregex "^[SU](MIN|MAX)v")>;
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def : InstRW<[M1WriteNMISC2], (instregex "^[SU](MIN|MAX)Pv")>;
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def : InstRW<[M1WriteNMISC3], (instregex "^[SU](MIN|MAX)Vv")>;
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def : InstRW<[M1WriteNMISC4], (instregex "^(MUL|SQR?DMULH)v")>;
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def : InstRW<[M1WriteNMISC4], (instregex "^ML[AS]v")>;
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def : InstRW<[M1WriteNMISC4], (instregex "^(S|U|SQD|SQRD)ML[AS][HL]v")>;
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def : InstRW<[M1WriteNMISC4], (instregex "^(S|U|SQD)MULLv")>;
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def : InstRW<[M1WriteNAL13], (instregex "^(S|SR|U|UR)SRAv")>;
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def : InstRW<[M1WriteNALU1], (instregex "^[SU]?SH(L|LL|R)2?v")>;
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def : InstRW<[M1WriteNALU1], (instregex "^S[LR]Iv")>;
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def : InstRW<[M1WriteNAL13], (instregex "^[SU]?(Q|QR|R)?SHR(N|U|UN)?2?v")>;
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def : InstRW<[M1WriteNAL13], (instregex "^[SU](Q|QR|R)SHLU?v")>;
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// ASIMD FP instructions.
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def : InstRW<[M1WriteNALU1], (instregex "^F(ABS|NEG)v")>;
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def : InstRW<[M1WriteNMISC3], (instregex "^F(ABD|ADD|SUB)v")>;
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def : InstRW<[M1WriteNEONA], (instregex "^FADDP")>;
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def : InstRW<[M1WriteNMISC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
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def : InstRW<[M1WriteFCVT3], (instregex "^[FVSU]CVTX?[AFLMNPZ][SU]?(_Int)?v")>;
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def : InstRW<[M1WriteFVAR15], (instregex "FDIVv.f32")>;
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def : InstRW<[M1WriteFVAR23], (instregex "FDIVv2f64")>;
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def : InstRW<[M1WriteFVAR15], (instregex "FSQRTv.f32")>;
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def : InstRW<[M1WriteFVAR23], (instregex "FSQRTv2f64")>;
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def : InstRW<[M1WriteNMISC1], (instregex "^F(MAX|MIN)(NM)?V?v")>;
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def : InstRW<[M1WriteNMISC2], (instregex "^F(MAX|MIN)(NM)?Pv")>;
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def : InstRW<[M1WriteFMAC4], (instregex "^FMULX?v")>;
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def : InstRW<[M1WriteFMAC5], (instregex "^FML[AS]v")>;
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def : InstRW<[M1WriteFCVT3], (instregex "^FRINT[AIMNPXZ]v")>;
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|
||||
// ASIMD miscellaneous instructions.
|
||||
def : InstRW<[M1WriteNALU1], (instregex "^RBITv")>;
|
||||
def : InstRW<[M1WriteNAL11], (instregex "^(BIF|BIT|BSL)v")>;
|
||||
def : InstRW<[M1WriteNALU1], (instregex "^CPY")>;
|
||||
def : InstRW<[M1WriteNEONB], (instregex "^DUPv.+gpr")>;
|
||||
def : InstRW<[M1WriteNALU1], (instregex "^DUPv.+lane")>;
|
||||
def : InstRW<[M1WriteNAL13], (instregex "^[SU]?Q?XTU?Nv")>;
|
||||
def : InstRW<[M1WriteNEONC], (instregex "^INSv.+gpr")>;
|
||||
def : InstRW<[M1WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev")>;
|
||||
def : InstRW<[M1WriteNMISC1], (instregex "^[FU](RECP|RSQRT)Xv")>;
|
||||
def : InstRW<[M1WriteFMAC5], (instregex "^F(RECP|RSQRT)Sv")>;
|
||||
def : InstRW<[M1WriteNALU1], (instregex "^REV(16|32|64)v")>;
|
||||
def : InstRW<[M1WriteNAL11], (instregex "^TB[LX]v8i8One")>;
|
||||
def : InstRW<[WriteSequence<[M1WriteNAL11], 2>],
|
||||
(instregex "^TB[LX]v8i8Two")>;
|
||||
def : InstRW<[WriteSequence<[M1WriteNAL11], 3>],
|
||||
(instregex "^TB[LX]v8i8Three")>;
|
||||
def : InstRW<[WriteSequence<[M1WriteNAL11], 4>],
|
||||
(instregex "^TB[LX]v8i8Four")>;
|
||||
def : InstRW<[M1WriteNAL12], (instregex "^TB[LX]v16i8One")>;
|
||||
def : InstRW<[WriteSequence<[M1WriteNAL12], 2>],
|
||||
(instregex "^TB[LX]v16i8Two")>;
|
||||
def : InstRW<[WriteSequence<[M1WriteNAL12], 3>],
|
||||
(instregex "^TB[LX]v16i8Three")>;
|
||||
def : InstRW<[WriteSequence<[M1WriteNAL12], 4>],
|
||||
(instregex "^TB[LX]v16i8Four")>;
|
||||
def : InstRW<[M1WriteNEOND], (instregex "^[SU]MOVv")>;
|
||||
def : InstRW<[M1WriteNALU1], (instregex "^INSv.+lane")>;
|
||||
def : InstRW<[M1WriteNALU1], (instregex "^(TRN|UZP)(1|2)(v8i8|v4i16|v2i32)")>;
|
||||
def : InstRW<[M1WriteNALU2], (instregex "^(TRN|UZP)(1|2)(v16i8|v8i16|v4i32|v2i64)")>;
|
||||
def : InstRW<[M1WriteNALU1], (instregex "^ZIP(1|2)v")>;
|
||||
|
||||
// ASIMD load instructions.
|
||||
|
||||
// ASIMD store instructions.
|
||||
|
||||
// Cryptography instructions.
|
||||
def : InstRW<[M1WriteNCRYPT1], (instregex "^AES")>;
|
||||
def : InstRW<[M1WriteNCRYPT1], (instregex "^PMUL")>;
|
||||
def : InstRW<[M1WriteNCRYPT1], (instregex "^SHA1(H|SU)")>;
|
||||
def : InstRW<[M1WriteNCRYPT5], (instregex "^SHA1[CMP]")>;
|
||||
def : InstRW<[M1WriteNCRYPT1], (instregex "^SHA256SU0")>;
|
||||
def : InstRW<[M1WriteNCRYPT5], (instregex "^SHA256(H|SU1)")>;
|
||||
|
||||
// CRC instructions.
|
||||
def : InstRW<[M1WriteC2], (instregex "^CRC32")>;
|
||||
|
||||
} // SchedModel = ExynosM1Model
|
||||
Loading…
Reference in New Issue