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simplify call code, remove pseudo ops for div and rem, track more loads and stores 

llvm-svn: 22322
This commit is contained in:
Andrew Lenharth 2005-07-01 19:12:13 +00:00
parent e8ab64b5c3
commit dd55b1566b
3 changed files with 92 additions and 80 deletions
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144
llvm/lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -612,7 +612,7 @@ static void getValueInfo(const Value* v, int& type, int& fun, int& offset)
offset = 0; offset = 0;
} else if (const GlobalValue* GV = dyn_cast<GlobalValue>(v)) { } else if (const GlobalValue* GV = dyn_cast<GlobalValue>(v)) {
type = 1; type = 1;
fun = 1; fun = 0;
const Module* M = GV->getParent(); const Module* M = GV->getParent();
int i = 0; int i = 0;
for(Module::const_global_iterator ii = M->global_begin(); &*ii != GV; ++ii) for(Module::const_global_iterator ii = M->global_begin(); &*ii != GV; ++ii)
@ -646,6 +646,8 @@ static void getValueInfo(const Value* v, int& type, int& fun, int& offset)
++i; ++i;
offset = i; offset = i;
} }
//type = 4: register spilling
//type = 5: global address loading or constant loading
} }
static int getUID() static int getUID()
@ -887,8 +889,15 @@ void AlphaISel::MoveFP2Int(unsigned src, unsigned dst, bool isDouble)
MachineFunction *F = BB->getParent(); MachineFunction *F = BB->getParent();
int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8); int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
if (EnableAlphaLSMark)
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
.addImm(getUID());
Opc = isDouble ? Alpha::STT : Alpha::STS; Opc = isDouble ? Alpha::STT : Alpha::STS;
BuildMI(BB, Opc, 3).addReg(src).addFrameIndex(FrameIdx).addReg(Alpha::F31); BuildMI(BB, Opc, 3).addReg(src).addFrameIndex(FrameIdx).addReg(Alpha::F31);
if (EnableAlphaLSMark)
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
.addImm(getUID());
Opc = isDouble ? Alpha::LDQ : Alpha::LDL; Opc = isDouble ? Alpha::LDQ : Alpha::LDL;
BuildMI(BB, Alpha::LDQ, 2, dst).addFrameIndex(FrameIdx).addReg(Alpha::F31); BuildMI(BB, Alpha::LDQ, 2, dst).addFrameIndex(FrameIdx).addReg(Alpha::F31);
} }
@ -907,8 +916,15 @@ void AlphaISel::MoveInt2FP(unsigned src, unsigned dst, bool isDouble)
MachineFunction *F = BB->getParent(); MachineFunction *F = BB->getParent();
int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8); int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
if (EnableAlphaLSMark)
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
.addImm(getUID());
Opc = isDouble ? Alpha::STQ : Alpha::STL; Opc = isDouble ? Alpha::STQ : Alpha::STL;
BuildMI(BB, Opc, 3).addReg(src).addFrameIndex(FrameIdx).addReg(Alpha::F31); BuildMI(BB, Opc, 3).addReg(src).addFrameIndex(FrameIdx).addReg(Alpha::F31);
if (EnableAlphaLSMark)
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
.addImm(getUID());
Opc = isDouble ? Alpha::LDT : Alpha::LDS; Opc = isDouble ? Alpha::LDT : Alpha::LDS;
BuildMI(BB, Opc, 2, dst).addFrameIndex(FrameIdx).addReg(Alpha::F31); BuildMI(BB, Opc, 2, dst).addFrameIndex(FrameIdx).addReg(Alpha::F31);
} }
@ -1260,25 +1276,17 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
getValueInfo(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue(), getValueInfo(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue(),
i, j, k); i, j, k);
if (GlobalAddressSDNode *GASD = GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address);
dyn_cast<GlobalAddressSDNode>(Address)) { if (GASD && !GASD->getGlobal()->isExternal()) {
if (GASD->getGlobal()->isExternal()) { Tmp1 = MakeReg(MVT::i64);
Tmp1 = SelectExpr(Address); AlphaLowering.restoreGP(BB);
if (EnableAlphaLSMark) BuildMI(BB, Alpha::LDAHr, 2, Tmp1)
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k) .addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
.addImm(getUID()); if (EnableAlphaLSMark)
BuildMI(BB, Opc, 2, Result).addImm(0).addReg(Tmp1); BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
} else { .addImm(getUID());
Tmp1 = MakeReg(MVT::i64); BuildMI(BB, GetRelVersion(Opc), 2, Result)
AlphaLowering.restoreGP(BB); .addGlobalAddress(GASD->getGlobal()).addReg(Tmp1);
BuildMI(BB, Alpha::LDAHr, 2, Tmp1)
.addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
if (EnableAlphaLSMark)
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
.addImm(getUID());
BuildMI(BB, GetRelVersion(Opc), 2, Result)
.addGlobalAddress(GASD->getGlobal()).addReg(Tmp1);
}
} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) { } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
AlphaLowering.restoreGP(BB); AlphaLowering.restoreGP(BB);
has_sym = true; has_sym = true;
@ -1313,7 +1321,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
has_sym = true; has_sym = true;
if (EnableAlphaLSMark) if (EnableAlphaLSMark)
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(0).addImm(0).addImm(0) BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
.addImm(getUID()); .addImm(getUID());
BuildMI(BB, Alpha::LDQl, 2, Result) BuildMI(BB, Alpha::LDQl, 2, Result)
@ -1321,6 +1329,19 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
.addReg(Alpha::R29); .addReg(Alpha::R29);
return Result; return Result;
case ISD::ExternalSymbol:
AlphaLowering.restoreGP(BB);
has_sym = true;
if (EnableAlphaLSMark)
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
.addImm(getUID());
BuildMI(BB, Alpha::LDQl, 2, Result)
.addExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol())
.addReg(Alpha::R29);
return Result;
case ISD::TAILCALL: case ISD::TAILCALL:
case ISD::CALL: case ISD::CALL:
{ {
@ -1393,27 +1414,12 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
} }
} }
//build the right kind of call //build the right kind of call
if (GlobalAddressSDNode *GASD = GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(N.getOperand(1));
dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) if (GASD && !GASD->getGlobal()->isExternal()) {
{ //use PC relative branch call
if (GASD->getGlobal()->isExternal()) {
//use safe calling convention
AlphaLowering.restoreGP(BB);
has_sym = true;
BuildMI(BB, Alpha::CALL, 1).addGlobalAddress(GASD->getGlobal());
} else {
//use PC relative branch call
AlphaLowering.restoreGP(BB);
BuildMI(BB, Alpha::BSR, 1, Alpha::R26)
.addGlobalAddress(GASD->getGlobal(),true);
}
}
else if (ExternalSymbolSDNode *ESSDN =
dyn_cast<ExternalSymbolSDNode>(N.getOperand(1)))
{
AlphaLowering.restoreGP(BB); AlphaLowering.restoreGP(BB);
has_sym = true; BuildMI(BB, Alpha::BSR, 1, Alpha::R26)
BuildMI(BB, Alpha::CALL, 1).addExternalSymbol(ESSDN->getSymbol(), true); .addGlobalAddress(GASD->getGlobal(),true);
} else { } else {
//no need to restore GP as we are doing an indirect call //no need to restore GP as we are doing an indirect call
Tmp1 = SelectExpr(N.getOperand(1)); Tmp1 = SelectExpr(N.getOperand(1));
@ -1886,26 +1892,27 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
} }
//else fall though //else fall though
case ISD::UREM: case ISD::UREM:
case ISD::SREM: case ISD::SREM: {
//FIXME: alpha really doesn't support any of these operations, const char* opstr = 0;
// the ops are expanded into special library calls with
// special calling conventions
//Restore GP because it is a call after all...
switch(opcode) { switch(opcode) {
case ISD::UREM: Opc = Alpha::REMQU; break; case ISD::UREM: opstr = "__remqu"; break;
case ISD::SREM: Opc = Alpha::REMQ; break; case ISD::SREM: opstr = "__remq"; break;
case ISD::UDIV: Opc = Alpha::DIVQU; break; case ISD::UDIV: opstr = "__divqu"; break;
case ISD::SDIV: Opc = Alpha::DIVQ; break; case ISD::SDIV: opstr = "__divq"; break;
} }
Tmp1 = SelectExpr(N.getOperand(0)); Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1)); Tmp2 = SelectExpr(N.getOperand(1));
SDOperand Addr =
ISelDAG->getExternalSymbol(opstr, AlphaLowering.getPointerTy());
Tmp3 = SelectExpr(Addr);
//set up regs explicitly (helps Reg alloc) //set up regs explicitly (helps Reg alloc)
BuildMI(BB, Alpha::BIS, 2, Alpha::R24).addReg(Tmp1).addReg(Tmp1); BuildMI(BB, Alpha::BIS, 2, Alpha::R24).addReg(Tmp1).addReg(Tmp1);
BuildMI(BB, Alpha::BIS, 2, Alpha::R25).addReg(Tmp2).addReg(Tmp2); BuildMI(BB, Alpha::BIS, 2, Alpha::R25).addReg(Tmp2).addReg(Tmp2);
AlphaLowering.restoreGP(BB); BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp3).addReg(Tmp3);
BuildMI(BB, Opc, 2).addReg(Alpha::R24).addReg(Alpha::R25); BuildMI(BB, Alpha::JSRs, 2, Alpha::R23).addReg(Alpha::R27).addImm(0);
BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R27).addReg(Alpha::R27); BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R27).addReg(Alpha::R27);
return Result; return Result;
}
case ISD::FP_TO_UINT: case ISD::FP_TO_UINT:
case ISD::FP_TO_SINT: case ISD::FP_TO_SINT:
@ -2095,6 +2102,9 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
Tmp1 = MakeReg(MVT::i64); Tmp1 = MakeReg(MVT::i64);
BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CPI) BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CPI)
.addReg(Alpha::R29); .addReg(Alpha::R29);
if (EnableAlphaLSMark)
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
.addImm(getUID());
BuildMI(BB, Alpha::LDQr, 2, Result).addConstantPoolIndex(CPI) BuildMI(BB, Alpha::LDQr, 2, Result).addConstantPoolIndex(CPI)
.addReg(Tmp1); .addReg(Tmp1);
} }
@ -2289,25 +2299,17 @@ void AlphaISel::Select(SDOperand N) {
getValueInfo(dyn_cast<SrcValueSDNode>(N.getOperand(3))->getValue(), getValueInfo(dyn_cast<SrcValueSDNode>(N.getOperand(3))->getValue(),
i, j, k); i, j, k);
if (GlobalAddressSDNode *GASD = GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address);
dyn_cast<GlobalAddressSDNode>(Address)) { if (GASD && !GASD->getGlobal()->isExternal()) {
if (GASD->getGlobal()->isExternal()) { Tmp2 = MakeReg(MVT::i64);
Tmp2 = SelectExpr(Address); AlphaLowering.restoreGP(BB);
if (EnableAlphaLSMark) BuildMI(BB, Alpha::LDAHr, 2, Tmp2)
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k) .addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
.addImm(getUID()); if (EnableAlphaLSMark)
BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(0).addReg(Tmp2); BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
} else { .addImm(getUID());
Tmp2 = MakeReg(MVT::i64); BuildMI(BB, GetRelVersion(Opc), 3).addReg(Tmp1)
AlphaLowering.restoreGP(BB); .addGlobalAddress(GASD->getGlobal()).addReg(Tmp2);
BuildMI(BB, Alpha::LDAHr, 2, Tmp2)
.addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
if (EnableAlphaLSMark)
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
.addImm(getUID());
BuildMI(BB, GetRelVersion(Opc), 3).addReg(Tmp1)
.addGlobalAddress(GASD->getGlobal()).addReg(Tmp2);
}
} else if(Address.getOpcode() == ISD::FrameIndex) { } else if(Address.getOpcode() == ISD::FrameIndex) {
if (EnableAlphaLSMark) if (EnableAlphaLSMark)
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k) BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)

12
llvm/lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -45,15 +45,6 @@ let Defs = [R29] in
let Uses = [R27] in let Uses = [R27] in
def LDGP : PseudoInstAlpha<(ops), "ldgp $$29, 0($$27)">; def LDGP : PseudoInstAlpha<(ops), "ldgp $$29, 0($$27)">;
let isCall = 1,
Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
F0, F1,
F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30],
Uses = [R29] in
def CALL : PseudoInstAlpha< (ops s64imm:$TARGET), "jsr $TARGET">; //Jump to subroutine
//RESULTS of these go to R27 //RESULTS of these go to R27
//These are also evil as the assembler expands them into calls //These are also evil as the assembler expands them into calls
let Uses = [R29], let Uses = [R29],
@ -305,6 +296,9 @@ let isCall = 1,
def JSR : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to subroutine def JSR : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to subroutine
def BSR : BForm<0x34, (ops GPRC:$RD, s21imm:$DISP), "bsr $RD,$DISP">; //Branch to subroutine def BSR : BForm<0x34, (ops GPRC:$RD, s21imm:$DISP), "bsr $RD,$DISP">; //Branch to subroutine
} }
let isCall = 1, Defs = [R24, R25, R27, R28], Uses = [R24, R25] in
def JSRs : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to div or rem
def JSR_COROUTINE : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS), "jsr_coroutine $RD,($RS),1">; //Jump to subroutine return def JSR_COROUTINE : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS), "jsr_coroutine $RD,($RS),1">; //Jump to subroutine return
def BR : BForm<0x30, (ops GPRC:$RD, s21imm:$DISP), "br $RD,$DISP">; //Branch def BR : BForm<0x30, (ops GPRC:$RD, s21imm:$DISP), "br $RD,$DISP">; //Branch

16
llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -31,6 +31,10 @@
#include <iostream> #include <iostream>
using namespace llvm; using namespace llvm;
namespace llvm {
extern cl::opt<bool> EnableAlphaLSMark;
}
//These describe LDAx //These describe LDAx
static const int IMM_LOW = -32768; static const int IMM_LOW = -32768;
static const int IMM_HIGH = 32767; static const int IMM_HIGH = 32767;
@ -50,6 +54,12 @@ static long getLower16(long l)
return l - h * IMM_MULT; return l - h * IMM_MULT;
} }
static int getUID()
{
static int id = 0;
return ++id;
}
AlphaRegisterInfo::AlphaRegisterInfo() AlphaRegisterInfo::AlphaRegisterInfo()
: AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP) : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP)
{ {
@ -68,6 +78,9 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
unsigned SrcReg, int FrameIdx) const { unsigned SrcReg, int FrameIdx) const {
//std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n"; //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
if (EnableAlphaLSMark)
BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(1)
.addImm(getUID());
if (getClass(SrcReg) == Alpha::FPRCRegisterClass) if (getClass(SrcReg) == Alpha::FPRCRegisterClass)
BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (getClass(SrcReg) == Alpha::GPRCRegisterClass) else if (getClass(SrcReg) == Alpha::GPRCRegisterClass)
@ -81,6 +94,9 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx) const{ unsigned DestReg, int FrameIdx) const{
//std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n"; //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
if (EnableAlphaLSMark)
BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2)
.addImm(getUID());
if (getClass(DestReg) == Alpha::FPRCRegisterClass) if (getClass(DestReg) == Alpha::FPRCRegisterClass)
BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (getClass(DestReg) == Alpha::GPRCRegisterClass) else if (getClass(DestReg) == Alpha::GPRCRegisterClass)