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[RISCV] Remove HadStdExtV and HasStdZve* Predicates from tablegen. 

No instructions should be using these. Everything should use
HasVInstructions* Predicates. Remove them so that they can't be
used by accident.
This commit is contained in:
Craig Topper 2022-01-20 12:53:12 -08:00
parent 40aef79db0
commit dd7b69a61f
3 changed files with 2 additions and 11 deletions
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9
llvm/lib/Target/RISCV/RISCV.td
View File

@ -166,43 +166,34 @@ def FeatureStdExtZve32x
"'Zve32x' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW)",
[FeatureStdExtZvl32b]>;
def HasStdExtZve32x : Predicate<"SubTarget->hasStdExtZve32x()">,
AssemblerPredicate<(all_of FeatureStdExtZve32x),
"'Zve32x' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW)">;
def FeatureStdExtZve32f
: SubtargetFeature<"experimental-zve32f", "HasStdExtZve32f", "true",
"'Zve32f' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW and F extension)",
[FeatureStdExtZve32x]>;
def HasStdExtZve32f : Predicate<"SubTarget->hasStdExtZve32f()">;
def FeatureStdExtZve64x
: SubtargetFeature<"experimental-zve64x", "HasStdExtZve64x", "true",
"'Zve64x' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW)", [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
def HasStdExtZve64x : Predicate<"SubTarget->hasStdExtZve64x()">;
def FeatureStdExtZve64f
: SubtargetFeature<"experimental-zve64f", "HasStdExtZve64f", "true",
"'Zve64f' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW and F extension)",
[FeatureStdExtZve32f, FeatureStdExtZve64x]>;
def HasStdExtZve64f : Predicate<"SubTarget->hasStdExtZve64f()">;
def FeatureStdExtZve64d
: SubtargetFeature<"experimental-zve64d", "HasStdExtZve64d", "true",
"'Zve64d' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW, F and D extension)",
[FeatureStdExtZve64f]>;
def HasStdExtZve64d : Predicate<"SubTarget->hasStdExtZve64d()">;
def FeatureStdExtV
: SubtargetFeature<"experimental-v", "HasStdExtV", "true",
"'V' (Vector Extension for Application Processors)",
[FeatureStdExtZvl128b, FeatureStdExtZve64d, FeatureStdExtF, FeatureStdExtD]>;
def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">;
def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">,
AssemblerPredicate<

2
llvm/lib/Target/RISCV/RISCVSchedRocket.td
View File

@ -17,7 +17,7 @@ def RocketModel : SchedMachineModel {
let LoadLatency = 3;
let MispredictPenalty = 3;
let CompleteModel = false;
let UnsupportedFeatures = [HasStdExtV, HasVInstructions, HasVInstructionsI64];
let UnsupportedFeatures = [HasVInstructions, HasVInstructionsI64];
}
//===----------------------------------------------------------------------===//

2
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
View File

@ -15,7 +15,7 @@ def SiFive7Model : SchedMachineModel {
let LoadLatency = 3;
let MispredictPenalty = 3;
let CompleteModel = 0;
let UnsupportedFeatures = [HasStdExtV];
let UnsupportedFeatures = [HasVInstructions];
}
// The SiFive7 microarchitecture has two pipelines: A and B.