[AArch64] Fix scheduler crash in fusion code.

Make sure we don't call getReg() on the first operand of instruction
without knowing that operand is actually a register.

(This codepath isn't enabled for most CPUs; only triggers on certain
CPUs, like Cortex-X1.)

Differential Revision: https://reviews.llvm.org/D136296

llvm/lib/Target/AArch64/AArch64MacroFusion.cpp

@@ -30,7 +30,8 @@ static bool isArithmeticBccPair(const MachineInstr *FirstMI,
 
   // If we're in CmpOnly mode, we only fuse arithmetic instructions that
   // discard their result.
-  if (CmpOnly && !(FirstMI->getOperand(0).getReg() == AArch64::XZR ||
+  if (CmpOnly && FirstMI->getOperand(0).isReg() &&
+      !(FirstMI->getOperand(0).getReg() == AArch64::XZR ||
         FirstMI->getOperand(0).getReg() == AArch64::WZR)) {
     return false;
   }

llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir

@@ -0,0 +1,29 @@
+# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mcpu=cortex-x1 -run-pass=machine-scheduler
+# Just ensure this doesn't crash.
+
+---
+name: crash
+tracksRegLiveness: true
+body: |
+  bb.0:
+    successors: %bb.1(0x00000000), %bb.2(0x80000000)
+    liveins: $w0, $x1
+
+    %1:gpr64common = COPY $x1
+    %0:gpr32common = COPY $w0
+    %3:gpr64sp = COPY $xzr
+    INLINEASM &"", 9 /* sideeffect mayload attdialect */, 196622 /* mem:m */, %3
+    %4:gpr32 = ADDSWri %0, 1, 0, implicit-def $nzcv
+    STRWui %4, %1, 0 :: (store (s32))
+    Bcc 3, %bb.2, implicit killed $nzcv
+    B %bb.1
+
+  bb.1:
+    successors:
+
+    ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+    ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+
+  bb.2:
+    RET_ReallyLR
+...