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Added cost of ZEROALL and ZEROUPPER instrs in btver2 cpu. 

Differential Revision https://reviews.llvm.org/D35834

llvm-svn: 309269
This commit is contained in:
Andrew V. Tischenko 2017-07-27 13:12:08 +00:00
parent 61c1bd5abc
commit e255526d0b
2 changed files with 13 additions and 2 deletions
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11
llvm/lib/Target/X86/X86ScheduleBtVer2.td
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@ -462,5 +462,16 @@ def WriteVSQRTYPSLd: SchedWriteRes<[JLAGU, JFPU1]> {
} }
def : InstRW<[WriteVSQRTYPSLd], (instregex "VSQRTPSYm")>; def : InstRW<[WriteVSQRTYPSLd], (instregex "VSQRTPSYm")>;
def WriteJVZEROALL: SchedWriteRes<[]> {
let Latency = 90;
let NumMicroOps = 73;
}
def : InstRW<[WriteJVZEROALL], (instregex "VZEROALL")>;
def WriteJVZEROUPPER: SchedWriteRes<[]> {
let Latency = 46;
let NumMicroOps = 37;
}
def : InstRW<[WriteJVZEROUPPER], (instregex "VZEROUPPER")>;
} // SchedModel } // SchedModel

4
llvm/test/CodeGen/X86/avx-schedule.ll
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@ -2850,7 +2850,7 @@ define void @test_zeroall() {
; ;
; BTVER2-LABEL: test_zeroall: ; BTVER2-LABEL: test_zeroall:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vzeroall ; BTVER2-NEXT: vzeroall # sched: [90:?]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_zeroall: ; ZNVER1-LABEL: test_zeroall:
@ -2875,7 +2875,7 @@ define void @test_zeroupper() {
; ;
; BTVER2-LABEL: test_zeroupper: ; BTVER2-LABEL: test_zeroupper:
; BTVER2: # BB#0: ; BTVER2: # BB#0:
; BTVER2-NEXT: vzeroupper ; BTVER2-NEXT: vzeroupper # sched: [46:?]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
; ;
; ZNVER1-LABEL: test_zeroupper: ; ZNVER1-LABEL: test_zeroupper: