[Hexagon] Updating XTYPE/PERM intrinsics.
llvm-svn: 228015
This commit is contained in:
Colin LeMahieu
parent
6544f815b3
commit
e5daf3abfe
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@ -109,6 +109,10 @@ class T_PRR_pat <InstHexagon MI, Intrinsic IntID>
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: Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
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(MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>;
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class T_PPQ_pat <InstHexagon MI, Intrinsic IntID>
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: Pat <(IntID I64:$Rs, I64:$Rt, (i32 PredRegs:$Ru)),
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(MI DoubleRegs:$Rs, DoubleRegs:$Rt, PredRegs:$Ru)>;
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class T_PR_pat <InstHexagon MI, Intrinsic IntID>
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: Pat <(IntID I64:$Rs, I32:$Rt),
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(MI DoubleRegs:$Rs, I32:$Rt)>;
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@ -1002,9 +1006,23 @@ def: T_RR_pat<C2_bitsclr, int_hexagon_C2_bitsclr>;
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def: T_RI_pat<C2_bitsclri, int_hexagon_C2_bitsclri>;
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def: T_RR_pat<C2_bitsset, int_hexagon_C2_bitsset>;
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// Vector shuffle
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def : T_PP_pat <S2_shuffeb, int_hexagon_S2_shuffeb>;
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def : T_PP_pat <S2_shuffob, int_hexagon_S2_shuffob>;
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def : T_PP_pat <S2_shuffeh, int_hexagon_S2_shuffeh>;
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def : T_PP_pat <S2_shuffoh, int_hexagon_S2_shuffoh>;
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// Vector truncate
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def : T_PP_pat <S2_vtrunewh, int_hexagon_S2_vtrunewh>;
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def : T_PP_pat <S2_vtrunowh, int_hexagon_S2_vtrunowh>;
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// Linear feedback-shift Iteration.
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def : T_PP_pat <S2_lfsp, int_hexagon_S2_lfsp>;
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// Vector splice
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def : T_PPQ_pat <S2_vsplicerb, int_hexagon_S2_vsplicerb>;
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def : T_PPI_pat <S2_vspliceib, int_hexagon_S2_vspliceib>;
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// Shift by immediate and add
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def : T_RRI_pat<S2_addasl_rrri, int_hexagon_S2_addasl_rrri>;
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@ -1061,6 +1079,16 @@ def : T_P_pat <A2_vconj, int_hexagon_A2_vconj>;
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// Vector Complex rotate
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def : T_PR_pat <S2_vcrotate, int_hexagon_S2_vcrotate>;
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/********************************************************************
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* STYPE/PERM *
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*********************************************************************/
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// Vector saturate without pack
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def : T_P_pat <S2_vsathb_nopack, int_hexagon_S2_vsathb_nopack>;
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def : T_P_pat <S2_vsathub_nopack, int_hexagon_S2_vsathub_nopack>;
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def : T_P_pat <S2_vsatwh_nopack, int_hexagon_S2_vsatwh_nopack>;
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def : T_P_pat <S2_vsatwuh_nopack, int_hexagon_S2_vsatwuh_nopack>;
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/********************************************************************
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* STYPE/SHIFT *
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*********************************************************************/
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@ -1082,9 +1110,28 @@ def : T_RR_pat <S2_lsl_r_r, int_hexagon_S2_lsl_r_r>;
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def : T_RR_pat <S2_asr_r_r_sat, int_hexagon_S2_asr_r_r_sat>;
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def : T_RR_pat <S2_asl_r_r_sat, int_hexagon_S2_asl_r_r_sat>;
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def : T_R_pat <S2_vsxtbh, int_hexagon_S2_vsxtbh>;
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def : T_R_pat <S2_vzxtbh, int_hexagon_S2_vzxtbh>;
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def : T_R_pat <S2_vsxthw, int_hexagon_S2_vsxthw>;
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def : T_R_pat <S2_vzxthw, int_hexagon_S2_vzxthw>;
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def : T_R_pat <S2_vsplatrh, int_hexagon_S2_vsplatrh>;
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def : T_R_pat <A2_sxtw, int_hexagon_A2_sxtw>;
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// Vector saturate and pack
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def : T_R_pat <S2_svsathb, int_hexagon_S2_svsathb>;
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def : T_R_pat <S2_svsathub, int_hexagon_S2_svsathub>;
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def : T_P_pat <S2_vsathub, int_hexagon_S2_vsathub>;
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def : T_P_pat <S2_vsatwh, int_hexagon_S2_vsatwh>;
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def : T_P_pat <S2_vsatwuh, int_hexagon_S2_vsatwuh>;
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def : T_P_pat <S2_vsathb, int_hexagon_S2_vsathb>;
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def : T_P_pat <S2_vtrunohb, int_hexagon_S2_vtrunohb>;
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def : T_P_pat <S2_vtrunehb, int_hexagon_S2_vtrunehb>;
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def : T_P_pat <S2_vrndpackwh, int_hexagon_S2_vrndpackwh>;
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def : T_P_pat <S2_vrndpackwhs, int_hexagon_S2_vrndpackwhs>;
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def : T_R_pat <S2_brev, int_hexagon_S2_brev>;
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def : T_R_pat <S2_vsplatrb, int_hexagon_S2_vsplatrb>;
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def : T_R_pat <A2_abs, int_hexagon_A2_abs>;
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def : T_R_pat <A2_abssat, int_hexagon_A2_abssat>;
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@ -1657,94 +1704,6 @@ class di_LDInstPI_diu4<string opc, Intrinsic IntID>
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[],
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"$src1 = $dst">;
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/********************************************************************
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* STYPE/PERM *
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*********************************************************************/
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// STYPE / PERM / Vector align.
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// Need custom lowering
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def HEXAGON_S2_valignib:
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di_SInst_didiu3 <"valignb", int_hexagon_S2_valignib>;
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def HEXAGON_S2_valignrb:
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di_SInst_didiqi <"valignb", int_hexagon_S2_valignrb>;
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// STYPE / PERM / Vector round and pack.
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def HEXAGON_S2_vrndpackwh:
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si_SInst_di <"vrndwh", int_hexagon_S2_vrndpackwh>;
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def HEXAGON_S2_vrndpackwhs:
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si_SInst_di_sat <"vrndwh", int_hexagon_S2_vrndpackwhs>;
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// STYPE / PERM / Vector saturate and pack.
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def HEXAGON_S2_svsathb:
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si_SInst_si <"vsathb", int_hexagon_S2_svsathb>;
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def HEXAGON_S2_vsathb:
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si_SInst_di <"vsathb", int_hexagon_S2_vsathb>;
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def HEXAGON_S2_svsathub:
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si_SInst_si <"vsathub", int_hexagon_S2_svsathub>;
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def HEXAGON_S2_vsathub:
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si_SInst_di <"vsathub", int_hexagon_S2_vsathub>;
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def HEXAGON_S2_vsatwh:
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si_SInst_di <"vsatwh", int_hexagon_S2_vsatwh>;
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def HEXAGON_S2_vsatwuh:
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si_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh>;
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// STYPE / PERM / Vector saturate without pack.
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def HEXAGON_S2_vsathb_nopack:
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di_SInst_di <"vsathb", int_hexagon_S2_vsathb_nopack>;
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def HEXAGON_S2_vsathub_nopack:
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di_SInst_di <"vsathub", int_hexagon_S2_vsathub_nopack>;
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def HEXAGON_S2_vsatwh_nopack:
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di_SInst_di <"vsatwh", int_hexagon_S2_vsatwh_nopack>;
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def HEXAGON_S2_vsatwuh_nopack:
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di_SInst_di <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
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// STYPE / PERM / Vector shuffle.
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def HEXAGON_S2_shuffeb:
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di_SInst_didi <"shuffeb", int_hexagon_S2_shuffeb>;
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def HEXAGON_S2_shuffeh:
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di_SInst_didi <"shuffeh", int_hexagon_S2_shuffeh>;
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def HEXAGON_S2_shuffob:
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di_SInst_didi <"shuffob", int_hexagon_S2_shuffob>;
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def HEXAGON_S2_shuffoh:
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di_SInst_didi <"shuffoh", int_hexagon_S2_shuffoh>;
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// STYPE / PERM / Vector splat bytes.
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def HEXAGON_S2_vsplatrb:
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si_SInst_si <"vsplatb", int_hexagon_S2_vsplatrb>;
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// STYPE / PERM / Vector splat halfwords.
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def HEXAGON_S2_vsplatrh:
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di_SInst_si <"vsplath", int_hexagon_S2_vsplatrh>;
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// STYPE / PERM / Vector splice.
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def Hexagon_S2_vsplicerb:
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di_SInst_didiqi <"vspliceb",int_hexagon_S2_vsplicerb>;
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def Hexagon_S2_vspliceib:
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di_SInst_didiu3 <"vspliceb",int_hexagon_S2_vspliceib>;
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// STYPE / PERM / Sign extend.
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def HEXAGON_S2_vsxtbh:
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di_SInst_si <"vsxtbh", int_hexagon_S2_vsxtbh>;
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def HEXAGON_S2_vsxthw:
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di_SInst_si <"vsxthw", int_hexagon_S2_vsxthw>;
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// STYPE / PERM / Truncate.
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def HEXAGON_S2_vtrunehb:
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si_SInst_di <"vtrunehb",int_hexagon_S2_vtrunehb>;
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def HEXAGON_S2_vtrunohb:
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si_SInst_di <"vtrunohb",int_hexagon_S2_vtrunohb>;
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def HEXAGON_S2_vtrunewh:
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di_SInst_didi <"vtrunewh",int_hexagon_S2_vtrunewh>;
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def HEXAGON_S2_vtrunowh:
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di_SInst_didi <"vtrunowh",int_hexagon_S2_vtrunowh>;
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// STYPE / PERM / Zero extend.
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def HEXAGON_S2_vzxtbh:
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di_SInst_si <"vzxtbh", int_hexagon_S2_vzxtbh>;
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def HEXAGON_S2_vzxthw:
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di_SInst_si <"vzxthw", int_hexagon_S2_vzxthw>;
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/********************************************************************
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* STYPE/PRED *
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*********************************************************************/
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@ -44,3 +44,209 @@ define i32 @A2_swiz(i32 %a) {
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ret i32 %z
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}
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; CHECK: r0 = swiz(r0)
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; Vector round and pack
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declare i32 @llvm.hexagon.S2.vrndpackwh(i64)
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define i32 @S2_vrndpackwh(i64 %a) {
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%z = call i32 @llvm.hexagon.S2.vrndpackwh(i64 %a)
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ret i32 %z
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}
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; CHECK: r0 = vrndwh(r1:0)
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declare i32 @llvm.hexagon.S2.vrndpackwhs(i64)
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define i32 @S2_vrndpackwhs(i64 %a) {
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%z = call i32 @llvm.hexagon.S2.vrndpackwhs(i64 %a)
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ret i32 %z
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}
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; CHECK: r0 = vrndwh(r1:0):sat
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; Vector saturate and pack
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declare i32 @llvm.hexagon.S2.vsathub(i64)
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define i32 @S2_vsathub(i64 %a) {
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%z = call i32 @llvm.hexagon.S2.vsathub(i64 %a)
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ret i32 %z
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}
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; CHECK: r0 = vsathub(r1:0)
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declare i32 @llvm.hexagon.S2.vsatwh(i64)
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define i32 @S2_vsatwh(i64 %a) {
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%z = call i32 @llvm.hexagon.S2.vsatwh(i64 %a)
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ret i32 %z
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}
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; CHECK: r0 = vsatwh(r1:0)
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declare i32 @llvm.hexagon.S2.vsatwuh(i64)
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define i32 @S2_vsatwuh(i64 %a) {
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%z = call i32 @llvm.hexagon.S2.vsatwuh(i64 %a)
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ret i32 %z
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}
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; CHECK: r0 = vsatwuh(r1:0)
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declare i32 @llvm.hexagon.S2.vsathb(i64)
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define i32 @S2_vsathb(i64 %a) {
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%z = call i32 @llvm.hexagon.S2.vsathb(i64 %a)
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ret i32 %z
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}
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; CHECK: r0 = vsathb(r1:0)
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declare i32 @llvm.hexagon.S2.svsathb(i32)
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define i32 @S2_svsathb(i32 %a) {
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%z = call i32 @llvm.hexagon.S2.svsathb(i32 %a)
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ret i32 %z
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}
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; CHECK: r0 = vsathb(r0)
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declare i32 @llvm.hexagon.S2.svsathub(i32)
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define i32 @S2_svsathub(i32 %a) {
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%z = call i32 @llvm.hexagon.S2.svsathub(i32 %a)
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ret i32 %z
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}
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; CHECK: r0 = vsathub(r0)
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; Vector saturate without pack
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declare i64 @llvm.hexagon.S2.vsathub.nopack(i64)
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define i64 @S2_vsathub_nopack(i64 %a) {
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%z = call i64 @llvm.hexagon.S2.vsathub.nopack(i64 %a)
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ret i64 %z
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}
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; CHECK: r1:0 = vsathub(r1:0)
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declare i64 @llvm.hexagon.S2.vsatwuh.nopack(i64)
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define i64 @S2_vsatwuh_nopack(i64 %a) {
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%z = call i64 @llvm.hexagon.S2.vsatwuh.nopack(i64 %a)
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ret i64 %z
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}
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; CHECK: r1:0 = vsatwuh(r1:0)
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declare i64 @llvm.hexagon.S2.vsatwh.nopack(i64)
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define i64 @S2_vsatwh_nopack(i64 %a) {
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%z = call i64 @llvm.hexagon.S2.vsatwh.nopack(i64 %a)
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ret i64 %z
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}
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; CHECK: r1:0 = vsatwh(r1:0)
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declare i64 @llvm.hexagon.S2.vsathb.nopack(i64)
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define i64 @S2_vsathb_nopack(i64 %a) {
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%z = call i64 @llvm.hexagon.S2.vsathb.nopack(i64 %a)
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ret i64 %z
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}
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; CHECK: r1:0 = vsathb(r1:0)
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; Vector shuffle
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declare i64 @llvm.hexagon.S2.shuffeb(i64, i64)
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define i64 @S2_shuffeb(i64 %a, i64 %b) {
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%z = call i64 @llvm.hexagon.S2.shuffeb(i64 %a, i64 %b)
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ret i64 %z
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}
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; CHECK: r1:0 = shuffeb(r1:0, r3:2)
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declare i64 @llvm.hexagon.S2.shuffob(i64, i64)
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define i64 @S2_shuffob(i64 %a, i64 %b) {
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%z = call i64 @llvm.hexagon.S2.shuffob(i64 %a, i64 %b)
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ret i64 %z
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}
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; CHECK: r1:0 = shuffob(r1:0, r3:2)
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declare i64 @llvm.hexagon.S2.shuffeh(i64, i64)
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define i64 @S2_shuffeh(i64 %a, i64 %b) {
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%z = call i64 @llvm.hexagon.S2.shuffeh(i64 %a, i64 %b)
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ret i64 %z
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}
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; CHECK: r1:0 = shuffeh(r1:0, r3:2)
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declare i64 @llvm.hexagon.S2.shuffoh(i64, i64)
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define i64 @S2_shuffoh(i64 %a, i64 %b) {
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%z = call i64 @llvm.hexagon.S2.shuffoh(i64 %a, i64 %b)
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ret i64 %z
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}
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; CHECK: r1:0 = shuffoh(r1:0, r3:2)
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; Vector splat bytes
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declare i32 @llvm.hexagon.S2.vsplatrb(i32)
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define i32 @S2_vsplatrb(i32 %a) {
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%z = call i32 @llvm.hexagon.S2.vsplatrb(i32 %a)
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ret i32 %z
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}
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; CHECK: r0 = vsplatb(r0)
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; Vector splat halfwords
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declare i64 @llvm.hexagon.S2.vsplatrh(i32)
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define i64 @S2_vsplatrh(i32 %a) {
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%z = call i64 @llvm.hexagon.S2.vsplatrh(i32 %a)
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ret i64 %z
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}
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; CHECK: = vsplath(r0)
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; Vector splice
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declare i64 @llvm.hexagon.S2.vspliceib(i64, i64, i32)
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define i64 @S2_vspliceib(i64 %a, i64 %b) {
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%z = call i64 @llvm.hexagon.S2.vspliceib(i64 %a, i64 %b, i32 0)
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ret i64 %z
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}
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; CHECK: r1:0 = vspliceb(r1:0, r3:2, #0)
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declare i64 @llvm.hexagon.S2.vsplicerb(i64, i64, i32)
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define i64 @S2_vsplicerb(i64 %a, i64 %b, i32 %c) {
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%z = call i64 @llvm.hexagon.S2.vsplicerb(i64 %a, i64 %b, i32 %c)
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ret i64 %z
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}
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; CHECK: r1:0 = vspliceb(r1:0, r3:2, p0)
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; Vector sign extend
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declare i64 @llvm.hexagon.S2.vsxtbh(i32)
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define i64 @S2_vsxtbh(i32 %a) {
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%z = call i64 @llvm.hexagon.S2.vsxtbh(i32 %a)
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ret i64 %z
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}
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; CHECK: = vsxtbh(r0)
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declare i64 @llvm.hexagon.S2.vsxthw(i32)
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define i64 @S2_vsxthw(i32 %a) {
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%z = call i64 @llvm.hexagon.S2.vsxthw(i32 %a)
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ret i64 %z
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}
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; CHECK: = vsxthw(r0)
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; Vector truncate
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declare i32 @llvm.hexagon.S2.vtrunohb(i64)
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define i32 @S2_vtrunohb(i64 %a) {
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%z = call i32 @llvm.hexagon.S2.vtrunohb(i64 %a)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vtrunohb(r1:0)
|
||||
|
||||
declare i32 @llvm.hexagon.S2.vtrunehb(i64)
|
||||
define i32 @S2_vtrunehb(i64 %a) {
|
||||
%z = call i32 @llvm.hexagon.S2.vtrunehb(i64 %a)
|
||||
ret i32 %z
|
||||
}
|
||||
; CHECK: r0 = vtrunehb(r1:0)
|
||||
|
||||
declare i64 @llvm.hexagon.S2.vtrunowh(i64, i64)
|
||||
define i64 @S2_vtrunowh(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.S2.vtrunowh(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vtrunowh(r1:0, r3:2)
|
||||
|
||||
declare i64 @llvm.hexagon.S2.vtrunewh(i64, i64)
|
||||
define i64 @S2_vtrunewh(i64 %a, i64 %b) {
|
||||
%z = call i64 @llvm.hexagon.S2.vtrunewh(i64 %a, i64 %b)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: r1:0 = vtrunewh(r1:0, r3:2)
|
||||
|
||||
; Vector zero extend
|
||||
declare i64 @llvm.hexagon.S2.vzxtbh(i32)
|
||||
define i64 @S2_vzxtbh(i32 %a) {
|
||||
%z = call i64 @llvm.hexagon.S2.vzxtbh(i32 %a)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: = vzxtbh(r0)
|
||||
|
||||
declare i64 @llvm.hexagon.S2.vzxthw(i32)
|
||||
define i64 @S2_vzxthw(i32 %a) {
|
||||
%z = call i64 @llvm.hexagon.S2.vzxthw(i32 %a)
|
||||
ret i64 %z
|
||||
}
|
||||
; CHECK: = vzxthw(r0)
|
||||
|
|
|
|||
Loading…
Reference in New Issue