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More 80 col violation. 

llvm-svn: 101806
This commit is contained in:
Evan Cheng 2010-04-19 19:17:44 +00:00
parent 6188093cca
commit e7c21a4242
1 changed files with 4 additions and 2 deletions
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6
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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@ -1406,7 +1406,8 @@ void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
if (NVTBits < EVTBits) {
Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), EVTBits - NVTBits)));
DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
EVTBits - NVTBits)));
} else {
Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
// The high part must be zero, make it explicit.
@ -1849,7 +1850,8 @@ void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
unsigned ExcessBits =
Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), ExcessBits)));
DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
ExcessBits)));
}
}