OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity

foldMemoryOperand() cannot fold tMOVrr sp into load / store in thumb mode. tLDRspi / tSTRspi cannot target / store high registers. 

llvm-svn: 33958
This commit is contained in:
Evan Cheng 2007-02-06 06:13:29 +00:00
parent 1b4b054cba
commit ea3308aef0
1 changed files with 19 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
llvm/lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -185,6 +185,19 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
abort(); abort();
} }
/// isLowRegister - Returns true if the register is low register r0-r7.
///
static bool isLowRegister(unsigned Reg) {
using namespace ARM;
switch (Reg) {
case R0: case R1: case R2: case R3:
case R4: case R5: case R6: case R7:
return true;
default:
return false;
}
}
MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
unsigned OpNum, int FI) const { unsigned OpNum, int FI) const {
unsigned Opc = MI->getOpcode(); unsigned Opc = MI->getOpcode();
@ -206,10 +219,16 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
case ARM::tMOVrr: { case ARM::tMOVrr: {
if (OpNum == 0) { // move -> store if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg(); unsigned SrcReg = MI->getOperand(1).getReg();
if (!isLowRegister(SrcReg))
// tSTRspi cannot take a high register operand.
break;
NewMI = BuildMI(TII.get(ARM::tSTRspi)).addReg(SrcReg).addFrameIndex(FI) NewMI = BuildMI(TII.get(ARM::tSTRspi)).addReg(SrcReg).addFrameIndex(FI)
.addImm(0); .addImm(0);
} else { // move -> load } else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg(); unsigned DstReg = MI->getOperand(0).getReg();
if (!isLowRegister(DstReg))
// tLDRspi cannot target a high register operand.
break;
NewMI = BuildMI(TII.get(ARM::tLDRspi), DstReg).addFrameIndex(FI) NewMI = BuildMI(TII.get(ARM::tLDRspi), DstReg).addFrameIndex(FI)
.addImm(0); .addImm(0);
} }
@ -316,19 +335,6 @@ void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
} }
} }
/// isLowRegister - Returns true if the register is low register r0-r7.
///
static bool isLowRegister(unsigned Reg) {
using namespace ARM;
switch (Reg) {
case R0: case R1: case R2: case R3:
case R4: case R5: case R6: case R7:
return true;
default:
return false;
}
}
/// calcNumMI - Returns the number of instructions required to materialize /// calcNumMI - Returns the number of instructions required to materialize
/// the specific add / sub r, c instruction. /// the specific add / sub r, c instruction.
static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,