If sp offset will be materialized in a register. Clear the offset field of str / ldr.
llvm-svn: 34010
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			@ -762,16 +762,18 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
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      return;
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    }
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    // If this is a thumb spill / restore, we will be using a constpool load to
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    // materialize the offset.
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    bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
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    if (AddrMode == ARMII::AddrModeTs && !isThumSpillRestore) {
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    if (AddrMode == ARMII::AddrModeTs) {
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      // Thumb tLDRspi, tSTRspi. These will change to instructions that use
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      // a different base register.
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      NumBits = 5;
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      Mask = (1 << NumBits) - 1;
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    }
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    // If this is a thumb spill / restore, we will be using a constpool load to
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    // materialize the offset.
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    if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
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      ImmOp.ChangeToImmediate(0);
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    else {
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      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
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      ImmedOffset = ImmedOffset & Mask;
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      if (isSub)
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