OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity

[AArch64][GlobalISel] Simplify a legalizer test. NFC. 

llvm-svn: 345307
This commit is contained in:
Volkan Keles 2018-10-25 20:01:19 +00:00
parent 3b4bbe7b0f
commit f28e81f6aa
1 changed files with 91 additions and 116 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

207
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
View File

@ -1,130 +1,105 @@
# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--"
define void @test_load(i8* %addr) {
entry:
ret void
}
define void @test_store(i8* %addr) {
entry:
ret void
}
...
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_load
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
- { id: 6, class: _ }
- { id: 7, class: _ }
- { id: 8, class: _ }
body: |
bb.0.entry:
liveins: $x0, $x1, $x2, $x3
liveins: $x0
; CHECK-LABEL: name: test_load
%0(p0) = COPY $x0
%1(s1) = G_LOAD %0 :: (load 1 from %ir.addr)
%9:_(s32) = G_ANYEXT %1
$w0 = COPY %9
; CHECK: %2:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
%2(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
%10:_(s32) = G_ANYEXT %2
$w0 = COPY %10
; CHECK: %3:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.addr)
%3(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
%11:_(s32) = G_ANYEXT %3
$w0 = COPY %11
; CHECK: %4:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.addr)
%4(s32) = G_LOAD %0 :: (load 4 from %ir.addr)
$w0 = COPY %4
; CHECK: %5:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
%5(s64) = G_LOAD %0 :: (load 8 from %ir.addr)
$x0 = COPY %5
%6(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
%12:_(s64) = G_PTRTOINT %6
$x0 = COPY %12
; CHECK: %7:_(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
%7(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
%13:_(s64) = G_BITCAST %7
$x0 = COPY %13
; CHECK: [[LOAD0:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.addr, align 16)
; CHECK: [[OFFSET1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP %0, [[OFFSET1]](s64)
; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load 8 from %ir.addr + 8)
; CHECK: %8:_(s128) = G_MERGE_VALUES [[LOAD0]](s64), [[LOAD1]](s64)
%8(s128) = G_LOAD %0(p0) :: (load 16 from %ir.addr)
%14:_(s64) = G_TRUNC %8
$x0 = COPY %14
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load 1)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s8)
; CHECK: $w0 = COPY [[ANYEXT]](s32)
; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load 1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s8)
; CHECK: $w0 = COPY [[ANYEXT1]](s32)
; CHECK: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load 2)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD2]](s16)
; CHECK: $w0 = COPY [[ANYEXT2]](s32)
; CHECK: $w0 = COPY [[ANYEXT1]](s32)
; CHECK: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 8)
; CHECK: $x0 = COPY [[LOAD3]](s64)
; CHECK: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8)
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[LOAD4]](p0)
; CHECK: $x0 = COPY [[PTRTOINT]](s64)
; CHECK: [[LOAD5:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load 8)
; CHECK: [[BITCAST:%[0-9]+]]:_(s64) = G_BITCAST [[LOAD5]](<2 x s32>)
; CHECK: $x0 = COPY [[BITCAST]](s64)
; CHECK: [[LOAD6:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 8, align 16)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
; CHECK: [[LOAD7:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8)
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[LOAD6]](s64), [[LOAD7]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[MV]](s128)
; CHECK: $x0 = COPY [[TRUNC]](s64)
%0:_(p0) = COPY $x0
%1:_(s1) = G_LOAD %0(p0) :: (load 1)
%2:_(s32) = G_ANYEXT %1(s1)
$w0 = COPY %2(s32)
%3:_(s8) = G_LOAD %0(p0) :: (load 1)
%4:_(s32) = G_ANYEXT %3(s8)
$w0 = COPY %4(s32)
%5:_(s16) = G_LOAD %0(p0) :: (load 2)
%6:_(s32) = G_ANYEXT %5(s16)
$w0 = COPY %6(s32)
%7:_(s32) = G_LOAD %0(p0) :: (load 4)
$w0 = COPY %4(s32)
%8:_(s64) = G_LOAD %0(p0) :: (load 8)
$x0 = COPY %8(s64)
%9:_(p0) = G_LOAD %0(p0) :: (load 8)
%10:_(s64) = G_PTRTOINT %9(p0)
$x0 = COPY %10(s64)
%11:_(<2 x s32>) = G_LOAD %0(p0) :: (load 8)
%12:_(s64) = G_BITCAST %11(<2 x s32>)
$x0 = COPY %12(s64)
%13:_(s128) = G_LOAD %0(p0) :: (load 16)
%14:_(s64) = G_TRUNC %13(s128)
$x0 = COPY %14(s64)
...
---
name: test_store
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
- { id: 6, class: _ }
- { id: 7, class: _ }
body: |
bb.0.entry:
liveins: $x0, $x1, $x2, $x3
liveins: $x0, $w1
; CHECK-LABEL: name: test_store
%0(p0) = COPY $x0
%1(s32) = COPY $w1
; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[B:%.*]]:_(s32) = COPY %1(s32)
; CHECK: [[COPY_C1:%.*]]:_(s32) = COPY [[C1]]
; CHECK: [[AND:%.*]]:_(s32) = G_AND [[B]], [[COPY_C1]]
; CHECK: [[BIT8:%.*]]:_(s8) = G_TRUNC [[AND]]
; CHECK: G_STORE [[BIT8]](s8), %0(p0) :: (store 1 into %ir.addr)
%2(s1) = G_TRUNC %1
G_STORE %2, %0 :: (store 1 into %ir.addr)
; CHECK: G_STORE %3(s8), %0(p0) :: (store 1 into %ir.addr)
%3(s8) = G_TRUNC %1
G_STORE %3, %0 :: (store 1 into %ir.addr)
; CHECK: G_STORE %4(s16), %0(p0) :: (store 2 into %ir.addr)
%4(s16) = G_TRUNC %1
G_STORE %4, %0 :: (store 2 into %ir.addr)
; CHECK: G_STORE %1(s32), %0(p0) :: (store 4 into %ir.addr)
G_STORE %1, %0 :: (store 4 into %ir.addr)
; CHECK: G_STORE %5(s64), %0(p0) :: (store 8 into %ir.addr)
%5(s64) = G_PTRTOINT %0(p0)
G_STORE %5, %0 :: (store 8 into %ir.addr)
; CHECK: G_STORE %0(p0), %0(p0) :: (store 8 into %ir.addr)
G_STORE %0(p0), %0(p0) :: (store 8 into %ir.addr)
; CHECK: G_STORE %5(s64), %0(p0) :: (store 8 into %ir.addr, align 16)
; CHECK: [[OFFSET1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP %0, [[OFFSET1]](s64)
; CHECK: G_STORE %6(s64), [[GEP1]](p0) :: (store 8 into %ir.addr + 8)
%6(s64) = G_PTRTOINT %0(p0)
%7(s128) = G_MERGE_VALUES %5, %6
G_STORE %7, %0 :: (store 16 into %ir.addr)
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[AND]](s32)
; CHECK: G_STORE [[TRUNC]](s8), [[COPY]](p0) :: (store 1)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; CHECK: G_STORE [[TRUNC1]](s8), [[COPY]](p0) :: (store 1)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK: G_STORE [[TRUNC2]](s16), [[COPY]](p0) :: (store 2)
; CHECK: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store 4)
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
; CHECK: G_STORE [[PTRTOINT]](s64), [[COPY]](p0) :: (store 8)
; CHECK: G_STORE [[COPY]](p0), [[COPY]](p0) :: (store 8)
; CHECK: [[PTRTOINT1:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
; CHECK: G_STORE [[PTRTOINT1]](s64), [[COPY]](p0) :: (store 8, align 16)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C1]](s64)
; CHECK: G_STORE [[PTRTOINT1]](s64), [[GEP]](p0) :: (store 8)
%0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1
%2:_(s1) = G_TRUNC %1(s32)
G_STORE %2(s1), %0(p0) :: (store 1)
%3:_(s8) = G_TRUNC %1(s32)
G_STORE %3(s8), %0(p0) :: (store 1)
%4:_(s16) = G_TRUNC %1(s32)
G_STORE %4(s16), %0(p0) :: (store 2)
G_STORE %1(s32), %0(p0) :: (store 4)
%5:_(s64) = G_PTRTOINT %0(p0)
G_STORE %5(s64), %0(p0) :: (store 8)
G_STORE %0(p0), %0(p0) :: (store 8)
%6:_(s64) = G_PTRTOINT %0(p0)
%7:_(s128) = G_MERGE_VALUES %6(s64), %6
G_STORE %7(s128), %0(p0) :: (store 16)
...