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[AVX512] Remove separate instruction and patterns for lowering ctlz_zero_undef. Change the operation for CTLZ_ZERO_UNDEF to Expand so SelectionDAG will convert them to CTLZ before lowering. 

llvm-svn: 256477
This commit is contained in:
Craig Topper 2015-12-27 21:33:50 +00:00
parent 4b1808d8e7
commit f3ed5c115c
2 changed files with 16 additions and 22 deletions
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35
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -1525,17 +1525,17 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
if (Subtarget->hasCDI()) {
setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Expand);
setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Expand);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
@ -1545,10 +1545,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Expand);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
@ -1559,10 +1559,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Expand);
}
} // Subtarget->hasCDI()
@ -1682,8 +1682,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
if (Subtarget->hasCDI()) {
setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Expand);
}
for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
@ -18001,9 +18001,6 @@ static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
unsigned NumBits = VT.getSizeInBits();
SDLoc dl(Op);
if (VT.isVector() && Subtarget->hasAVX512())
return LowerVectorCTLZ_AVX512(Op, DAG);
Op = Op.getOperand(0);
if (VT == MVT::i8) {
// Zero extend to i32 since there is not an i8 bsr.

3
llvm/lib/Target/X86/X86InstrAVX512.td
View File

@ -7184,9 +7184,6 @@ def : Pat<(xor
multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
let isCodeGenOnly = 1 in
defm NAME#_UNDEF : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr,
ctlz_zero_undef, prd>;
}
defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;