OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity

[X86] Fix combineVectorCompareAndMaskUnaryOp regression after 0e8e731449

This commit is contained in:
Fangrui Song 2020-05-10 18:21:18 -07:00
parent 689486dc2a
commit f40fc7b8d6
2 changed files with 32 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -45586,7 +45586,8 @@ static SDValue combineVectorCompareAndMaskUnaryOp(SDNode *N,
unsigned NumEltBits = VT.getScalarSizeInBits();
SDValue Op0 = N->getOperand(IsStrict ? 1 : 0);
if (!VT.isVector() || Op0.getOpcode() != ISD::AND ||
DAG.ComputeNumSignBits(Op0.getOperand(0)) != NumEltBits)
DAG.ComputeNumSignBits(Op0.getOperand(0)) != NumEltBits ||
VT.getSizeInBits() != Op0.getValueSizeInBits())
return SDValue();
// Now check that the other operand of the AND is a constant. We could

30
llvm/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll
View File

@ -138,3 +138,33 @@ define <4 x float> @foo6(<4 x i32> %a0, <4 x i32> %a1) {
%6 = uitofp <4 x i32> %5 to <4 x float>
ret <4 x float> %6
}
define <4 x float> @foo7(<4 x i64> %a) {
; CHECK-LABEL: LCPI7_0:
; CHECK-NEXT: .byte 0 ## 0x0
; CHECK-NEXT: .byte 255 ## 0xff
; CHECK-NEXT: .byte 0 ## 0x0
; CHECK-NEXT: .byte 0 ## 0x0
; CHECK-NEXT: .byte 0 ## 0x0
; CHECK-NEXT: .byte 255 ## 0xff
; CHECK-NEXT: .byte 0 ## 0x0
; CHECK-NEXT: .byte 0 ## 0x0
; CHECK-NEXT: .byte 0 ## 0x0
; CHECK-NEXT: .byte 255 ## 0xff
; CHECK-NEXT: .byte 0 ## 0x0
; CHECK-NEXT: .byte 0 ## 0x0
; CHECK-NEXT: .byte 0 ## 0x0
; CHECK-NEXT: .byte 255 ## 0xff
; CHECK-NEXT: .byte 0 ## 0x0
; CHECK-NEXT: .byte 0 ## 0x0
; CHECK-LABEL: foo7:
; CHECK: ## %bb.0:
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
; CHECK-NEXT: cvtdq2ps %xmm0, %xmm0
; CHECK-NEXT: retq
%b = and <4 x i64> %a, <i64 4278255360, i64 4278255360, i64 4278255360, i64 4278255360>
%c = and <4 x i64> %b, <i64 65535, i64 65535, i64 65535, i64 65535>
%d = uitofp <4 x i64> %c to <4 x float>
ret <4 x float> %d
}