OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity

ARM64: add i64 scalar pattern for @llvm.arm64.abs 

This will be used by the Clang front-end code for vabsd_s64.

llvm-svn: 205202
This commit is contained in:
Tim Northover 2014-03-31 15:46:17 +00:00
parent 759c71d621
commit f48103618e
4 changed files with 12 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/include/llvm/IR/IntrinsicsARM64.td
View File

@ -326,7 +326,7 @@ let Properties = [IntrNoMem] in {
def int_arm64_neon_sqxtun : AdvSIMD_1VectorArg_Narrow_Intrinsic; def int_arm64_neon_sqxtun : AdvSIMD_1VectorArg_Narrow_Intrinsic;
// Vector Absolute Value // Vector Absolute Value
def int_arm64_neon_abs : AdvSIMD_1VectorArg_Intrinsic; def int_arm64_neon_abs : AdvSIMD_1IntArg_Intrinsic;
// Vector Saturating Absolute Value // Vector Saturating Absolute Value
def int_arm64_neon_sqabs : AdvSIMD_1IntArg_Intrinsic; def int_arm64_neon_sqabs : AdvSIMD_1IntArg_Intrinsic;

3
llvm/lib/Target/ARM64/ARM64InstrFormats.td
View File

@ -5102,6 +5102,9 @@ multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
SDPatternOperator OpNode = null_frag> { SDPatternOperator OpNode = null_frag> {
def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm, def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
[(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>; [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
(!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
} }
multiclass SIMDTwoScalarSD<bit U, bit S, bits<5> opc, string asm> { multiclass SIMDTwoScalarSD<bit U, bit S, bits<5> opc, string asm> {

7
llvm/lib/Target/ARM64/ARM64InstrInfo.td
View File

@ -2052,13 +2052,6 @@ defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", ARM64cmlez>;
defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", ARM64cmltz>; defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", ARM64cmltz>;
defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>; defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>; defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
def : Pat<(v2f32 (int_arm64_neon_abs (v2f32 V64:$Rn))),
(FABSv2f32 V64:$Rn)>;
def : Pat<(v4f32 (int_arm64_neon_abs (v4f32 V128:$Rn))),
(FABSv4f32 V128:$Rn)>;
def : Pat<(v2f64 (int_arm64_neon_abs (v2f64 V128:$Rn))),
(FABSv2f64 V128:$Rn)>;
defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>; defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", ARM64fcmgez>; defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", ARM64fcmgez>;

8
llvm/test/CodeGen/ARM64/vabs.ll
View File

@ -452,6 +452,13 @@ define <1 x i64> @abs_1d(<1 x i64> %A) nounwind {
ret <1 x i64> %abs ret <1 x i64> %abs
} }
define i64 @abs_1d_honestly(i64 %A) nounwind {
; CHECK-LABEL: abs_1d_honestly:
; CHECK: abs d0, d0
%abs = call i64 @llvm.arm64.neon.abs.i64(i64 %A)
ret i64 %abs
}
declare <8 x i8> @llvm.arm64.neon.abs.v8i8(<8 x i8>) nounwind readnone declare <8 x i8> @llvm.arm64.neon.abs.v8i8(<8 x i8>) nounwind readnone
declare <16 x i8> @llvm.arm64.neon.abs.v16i8(<16 x i8>) nounwind readnone declare <16 x i8> @llvm.arm64.neon.abs.v16i8(<16 x i8>) nounwind readnone
declare <4 x i16> @llvm.arm64.neon.abs.v4i16(<4 x i16>) nounwind readnone declare <4 x i16> @llvm.arm64.neon.abs.v4i16(<4 x i16>) nounwind readnone
@ -459,6 +466,7 @@ declare <8 x i16> @llvm.arm64.neon.abs.v8i16(<8 x i16>) nounwind readnone
declare <2 x i32> @llvm.arm64.neon.abs.v2i32(<2 x i32>) nounwind readnone declare <2 x i32> @llvm.arm64.neon.abs.v2i32(<2 x i32>) nounwind readnone
declare <4 x i32> @llvm.arm64.neon.abs.v4i32(<4 x i32>) nounwind readnone declare <4 x i32> @llvm.arm64.neon.abs.v4i32(<4 x i32>) nounwind readnone
declare <1 x i64> @llvm.arm64.neon.abs.v1i64(<1 x i64>) nounwind readnone declare <1 x i64> @llvm.arm64.neon.abs.v1i64(<1 x i64>) nounwind readnone
declare i64 @llvm.arm64.neon.abs.i64(i64) nounwind readnone
define <8 x i16> @sabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind { define <8 x i16> @sabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind {
;CHECK-LABEL: sabal8h: ;CHECK-LABEL: sabal8h: