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[ARM GlobalISel] Add inst selector tests for G_FPTOSI and G_FPTOUI 

The work is done by the TableGen'erated code.

llvm-svn: 323728
This commit is contained in:
Diana Picus 2018-01-30 07:55:02 +00:00
parent a2da03022c
commit f5ad62d921
1 changed files with 113 additions and 0 deletions
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113
llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
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@ -33,6 +33,11 @@
define void @test_fpext_s32_to_s64() #0 { ret void }
define void @test_fptrunc_s64_to_s32() #0 {ret void }
define void @test_fptosi_s32() #0 { ret void }
define void @test_fptosi_s64() #0 { ret void }
define void @test_fptoui_s32() #0 { ret void }
define void @test_fptoui_s64() #0 { ret void }
define void @test_sub_s32() { ret void }
define void @test_sub_imm_s32() { ret void }
define void @test_sub_rev_imm_s32() { ret void }
@ -785,6 +790,114 @@ body: |
; CHECK: BX_RET 14, %noreg, implicit %s0
...
---
name: test_fptosi_s32
# CHECK-LABEL: name: test_fptosi_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: %s0
%0(s32) = COPY %s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
%1(s32) = G_FPTOSI %0(s32)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZS [[VREGX]], 14, %noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
%r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, %noreg, implicit %r0
...
---
name: test_fptosi_s64
# CHECK-LABEL: name: test_fptosi_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: %d0
%0(s64) = COPY %d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
%1(s32) = G_FPTOSI %0(s64)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZD [[VREGX]], 14, %noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
%r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, %noreg, implicit %r0
...
---
name: test_fptoui_s32
# CHECK-LABEL: name: test_fptoui_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: %s0
%0(s32) = COPY %s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
%1(s32) = G_FPTOUI %0(s32)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZS [[VREGX]], 14, %noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
%r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, %noreg, implicit %r0
...
---
name: test_fptoui_s64
# CHECK-LABEL: name: test_fptoui_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: %d0
%0(s64) = COPY %d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
%1(s32) = G_FPTOUI %0(s64)
; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZD [[VREGX]], 14, %noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
%r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, %noreg, implicit %r0
...
---
name: test_sub_s32
# CHECK-LABEL: name: test_sub_s32
legalized: true