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[AMDGPU] Add a MIR test for D125567

This commit is contained in:
Jay Foad 2022-05-17 16:50:08 +01:00
parent d8f4f1027a
commit f84741d8bf
1 changed files with 242 additions and 0 deletions
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llvm/test/CodeGen/AMDGPU/gfx10-shrink-mad-fma.mir Normal file
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GFX10
---
name: mad_cvv_f32
body: |
bb.0:
; GFX10-LABEL: name: mad_cvv_f32
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_MADMK_F32_:%[0-9]+]]:vgpr_32 = V_MADMK_F32 [[DEF]], 1092616192, [[DEF1]], implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_MADMK_F32_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = V_MAD_F32_e64 0, 1092616192, 0, %0, 0, %1, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...
---
name: mad_vcv_f32
body: |
bb.0:
; GFX10-LABEL: name: mad_vcv_f32
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_MADMK_F32_:%[0-9]+]]:vgpr_32 = V_MADMK_F32 [[DEF]], 1092616192, [[DEF1]], implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_MADMK_F32_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = V_MAD_F32_e64 0, %0, 0, 1092616192, 0, %1, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...
---
name: mad_vvc_f32
body: |
bb.0:
; GFX10-LABEL: name: mad_vvc_f32
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_MADAK_F32_:%[0-9]+]]:vgpr_32 = V_MADAK_F32 [[DEF]], [[DEF1]], 1092616192, implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_MADAK_F32_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = V_MAD_F32_e64 0, %0, 0, %1, 0, 1092616192, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...
---
name: mad_vsc_f32
body: |
bb.0:
; GFX10-LABEL: name: mad_vsc_f32
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_MADAK_F32_:%[0-9]+]]:vgpr_32 = V_MADAK_F32 [[DEF1]], [[DEF]], 1092616192, implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_MADAK_F32_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_32 = IMPLICIT_DEF
%2:vgpr_32 = V_MAD_F32_e64 0, %0, 0, %1, 0, 1092616192, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...
---
name: fma_cvv_f32
body: |
bb.0:
; GFX10-LABEL: name: fma_cvv_f32
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_FMAMK_F32_:%[0-9]+]]:vgpr_32 = V_FMAMK_F32 [[DEF]], 1092616192, [[DEF1]], implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_FMAMK_F32_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = V_FMA_F32_e64 0, 1092616192, 0, %0, 0, %1, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...
---
name: fma_vcv_f32
body: |
bb.0:
; GFX10-LABEL: name: fma_vcv_f32
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_FMAMK_F32_:%[0-9]+]]:vgpr_32 = V_FMAMK_F32 [[DEF]], 1092616192, [[DEF1]], implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_FMAMK_F32_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = V_FMA_F32_e64 0, %0, 0, 1092616192, 0, %1, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...
---
name: fma_vvc_f32
body: |
bb.0:
; GFX10-LABEL: name: fma_vvc_f32
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_FMAAK_F32_:%[0-9]+]]:vgpr_32 = V_FMAAK_F32 [[DEF]], [[DEF1]], 1092616192, implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_FMAAK_F32_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = V_FMA_F32_e64 0, %0, 0, %1, 0, 1092616192, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...
---
name: fma_vsc_f32
body: |
bb.0:
; GFX10-LABEL: name: fma_vsc_f32
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_FMAAK_F32_:%[0-9]+]]:vgpr_32 = V_FMAAK_F32 [[DEF1]], [[DEF]], 1092616192, implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_FMAAK_F32_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_32 = IMPLICIT_DEF
%2:vgpr_32 = V_FMA_F32_e64 0, %0, 0, %1, 0, 1092616192, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...
---
name: mad_cvv_f16
body: |
bb.0:
; GFX10-LABEL: name: mad_cvv_f16
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_MAD_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAD_F16_e64 0, 18688, 0, [[DEF]], 0, [[DEF1]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_MAD_F16_e64_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = V_MAD_F16_e64 0, 18688, 0, %0, 0, %1, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...
---
name: mad_vcv_f16
body: |
bb.0:
; GFX10-LABEL: name: mad_vcv_f16
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_MAD_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAD_F16_e64 0, [[DEF]], 0, 18688, 0, [[DEF1]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_MAD_F16_e64_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = V_MAD_F16_e64 0, %0, 0, 18688, 0, %1, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...
---
name: mad_vvc_f16
body: |
bb.0:
; GFX10-LABEL: name: mad_vvc_f16
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_MAD_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAD_F16_e64 0, [[DEF]], 0, [[DEF1]], 0, 18688, 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_MAD_F16_e64_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = V_MAD_F16_e64 0, %0, 0, %1, 0, 18688, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...
---
name: mad_vsc_f16
body: |
bb.0:
; GFX10-LABEL: name: mad_vsc_f16
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_MAD_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAD_F16_e64 0, [[DEF]], 0, [[DEF1]], 0, 18688, 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_MAD_F16_e64_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_32 = IMPLICIT_DEF
%2:vgpr_32 = V_MAD_F16_e64 0, %0, 0, %1, 0, 18688, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...
---
name: fma_cvv_f16
body: |
bb.0:
; GFX10-LABEL: name: fma_cvv_f16
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_FMA_F16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_e64 0, 18688, 0, [[DEF]], 0, [[DEF1]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_FMA_F16_e64_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = V_FMA_F16_e64 0, 18688, 0, %0, 0, %1, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...
---
name: fma_vcv_f16
body: |
bb.0:
; GFX10-LABEL: name: fma_vcv_f16
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_FMA_F16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_e64 0, [[DEF]], 0, 18688, 0, [[DEF1]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_FMA_F16_e64_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = V_FMA_F16_e64 0, %0, 0, 18688, 0, %1, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...
---
name: fma_vvc_f16
body: |
bb.0:
; GFX10-LABEL: name: fma_vvc_f16
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_FMA_F16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_e64 0, [[DEF]], 0, [[DEF1]], 0, 18688, 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_FMA_F16_e64_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:vgpr_32 = IMPLICIT_DEF
%2:vgpr_32 = V_FMA_F16_e64 0, %0, 0, %1, 0, 18688, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...
---
name: fma_vsc_f16
body: |
bb.0:
; GFX10-LABEL: name: fma_vsc_f16
; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GFX10-NEXT: [[V_FMA_F16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_e64 0, [[DEF]], 0, [[DEF1]], 0, 18688, 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: SI_RETURN implicit [[V_FMA_F16_e64_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_32 = IMPLICIT_DEF
%2:vgpr_32 = V_FMA_F16_e64 0, %0, 0, %1, 0, 18688, 0, 0, implicit $mode, implicit $exec
SI_RETURN implicit %2
...