From fae8788cfaf6e0de60f9dfe2cf67131f2bdc5bf0 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 2 Feb 2018 21:59:46 +0000 Subject: [PATCH] [X86] Prefer to create a ISD::SETCC over X86ISD::PCMPEQ in combineVectorSizedSetCCEquality. This is running pre-legalize, we should try to use target independent nodes. This will give the best opportunity for target independent optimizations. llvm-svn: 324147 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 92c7094841eb..c63471df507c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -36477,13 +36477,13 @@ static SDValue combineVectorSizedSetCCEquality(SDNode *SetCC, SelectionDAG &DAG, SDValue B = DAG.getBitcast(VecVT, X.getOperand(0).getOperand(1)); SDValue C = DAG.getBitcast(VecVT, X.getOperand(1).getOperand(0)); SDValue D = DAG.getBitcast(VecVT, X.getOperand(1).getOperand(1)); - SDValue Cmp1 = DAG.getNode(X86ISD::PCMPEQ, DL, VecVT, A, B); - SDValue Cmp2 = DAG.getNode(X86ISD::PCMPEQ, DL, VecVT, C, D); + SDValue Cmp1 = DAG.getSetCC(DL, VecVT, A, B, ISD::SETEQ); + SDValue Cmp2 = DAG.getSetCC(DL, VecVT, C, D, ISD::SETEQ); Cmp = DAG.getNode(ISD::AND, DL, VecVT, Cmp1, Cmp2); } else { SDValue VecX = DAG.getBitcast(VecVT, X); SDValue VecY = DAG.getBitcast(VecVT, Y); - Cmp = DAG.getNode(X86ISD::PCMPEQ, DL, VecVT, VecX, VecY); + Cmp = DAG.getSetCC(DL, VecVT, VecX, VecY, ISD::SETEQ); } // If all bytes match (bitmask is 0x(FFFF)FFFF), that's equality. // setcc i128 X, Y, eq --> setcc (pmovmskb (pcmpeqb X, Y)), 0xFFFF, eq