parent
608d92c943
commit
fd10869d4b
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@ -614,17 +614,17 @@ def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
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// FIXME: Add actual movcc in IT blocks for Thumb2.
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// FIXME: Add actual movcc in IT blocks for Thumb2.
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let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
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let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
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def tMOVCCr :
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def tMOVCCr :
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PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), IIC_iALU,
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PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
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"@ tMOVCCr $cc",
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NoItinerary, "@ tMOVCCr $cc",
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[/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
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[/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
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// tLEApcrel - Load a pc-relative address into a register without offending the
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// tLEApcrel - Load a pc-relative address into a register without offending the
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// assembler.
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// assembler.
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def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label), IIC_iALU,
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def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label), IIC_iALU,
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"adr $dst, #$label", []>;
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"adr $dst, #$label", []>;
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def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, lane_cst:$id), IIC_iALU,
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def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, lane_cst:$id),
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"adr $dst, #${label}_${id}", []>;
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IIC_iALU, "adr $dst, #${label}_${id}", []>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// TLS Instructions
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// TLS Instructions
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