[mlir] Fixup python bindings after splitting cf ops from std.

mlir/python/CMakeLists.txt

@@ -72,6 +72,14 @@ declare_mlir_dialect_python_bindings(
     dialects/_builtin_ops_ext.py
   DIALECT_NAME builtin)
 
+declare_mlir_dialect_python_bindings(
+  ADD_TO_PARENT MLIRPythonSources.Dialects
+  ROOT_DIR "${CMAKE_CURRENT_SOURCE_DIR}/mlir"
+  TD_FILE dialects/ControlFlowOps.td
+  SOURCES
+    dialects/cf.py
+  DIALECT_NAME cf)
+
 declare_mlir_dialect_python_bindings(
   ADD_TO_PARENT MLIRPythonSources.Dialects
   ROOT_DIR "${CMAKE_CURRENT_SOURCE_DIR}/mlir"

mlir/python/mlir/dialects/ControlFlowOps.td

@@ -0,0 +1,15 @@
+//===-- ControlFlowOps.td - Python ControlFlowOps bindings -*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#ifndef PYTHON_BINDINGS_CONTROL_FLOW_OPS
+#define PYTHON_BINDINGS_CONTROL_FLOW_OPS
+
+include "mlir/Bindings/Python/Attributes.td"
+include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.td"
+
+#endif

mlir/python/mlir/dialects/cf.py

@@ -0,0 +1,5 @@
+#  Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+#  See https://llvm.org/LICENSE.txt for license information.
+#  SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+
+from ._cf_ops_gen import *

mlir/test/python/ir/blocks.py

@@ -5,6 +5,7 @@ import io
 import itertools
 from mlir.ir import *
 from mlir.dialects import builtin
+from mlir.dialects import cf
 # Note: std dialect needed for terminators.
 from mlir.dialects import std
 
@@ -43,11 +44,11 @@ def testBlockCreation():
 
       with InsertionPoint(entry_block) as entry_ip:
         assert entry_ip.block == entry_block
-        std.BranchOp([i16_arg], dest=middle_block)
+        cf.BranchOp([i16_arg], dest=middle_block)
 
       with InsertionPoint(middle_block) as middle_ip:
         assert middle_ip.block == middle_block
-        std.BranchOp([i32_arg], dest=successor_block)
+        cf.BranchOp([i32_arg], dest=successor_block)
     print(module.operation)
     # Ensure region back references are coherent.
     assert entry_block.region == middle_block.region == successor_block.region