Commit Graph

4447 Commits

Author SHA1 Message Date
wenhu1024 c20186f995
[VENTUS][fix] enable cts recognize generic keywords (#179)
When run cts generic_address_space test, the clBuildProgram always failed.
    Therefore, add option to recognize the generic keywords.
2025-07-04 11:13:06 +08:00
zhoujing 198eea9938 [VENTUS][feat] Support varadic function && enable address space in vastart/vaend 2023-08-08 15:45:41 +08:00
zhoujing 6f502d2c33 [VENTUS][RISCV][fix] Set correct datalayout for different language options 2023-07-25 16:55:05 +08:00
zhoujing b8223e72bd [VENTUS][RISCV][feat] Building libclc library into object file other than archive file
In our previous design, the libclc library is built into static library which make the generated
ELF file having a large size, now we change compiler and linker option to make generated ELF file size much smaller, detail information can be seen in this pull request https://github.com/THU-DSP-LAB/pocl/pull/11
2023-07-17 21:39:02 +08:00
zhoujing 760e86baf2 [VENTUS][RISCV][fix&feat] Add cl_khr_fp64 support and add missing header file 2023-07-13 09:21:50 +08:00
zhoujing ec224ea8a4 [VENTUS][RISCV][feat] Add `cl_khr_byte_addressable_store` feature 2023-06-29 11:02:17 +08:00
zhoujing 2126d76353 [VENTUS][RISCV][fix] Fix IR datalayout reset bugs 2023-06-28 22:36:58 +08:00
zhoujing 8c7f5a3c28 [VENTUS][RISCV][fix] Fix instructuions which contain 5 bits unsigned immediate asmParser && pattern bug 2023-05-26 17:52:36 +08:00
zhoujingya 8ba248d102 [VENTUS][RISCV] Add vararg support
Because ventus riscv is designed specially for OpenCL language, we originally add or remove some language features mainly for serving OpenCL, but we now need to add customized `printf` function which is expected to be written in C, so we need also to add support for C language features in current ventus

Signed-off-by: zhoujingya <jing.zhou@terapines.com>
2023-04-13 15:00:35 +08:00
zhoujingya 553e65dcf7 Change barrier and work_group_barrier into builtin functions 2023-03-14 10:38:22 +08:00
Aries c4e5ff31b2 Fix OpenCL address space mapping 2023-01-16 10:28:37 +08:00
Aries 0b43b70327 Fix bug in addressing space mapping 2023-01-03 10:45:58 +08:00
Aries 27111da83b Add OpenCL addressing space to target addressing space mapping 2022-12-20 14:49:50 +08:00
Aries dee3135130 Drafting divergent related code, not working yet. 2022-12-19 18:11:34 +08:00
Fangrui Song a996cc217c Remove unused #include "llvm/ADT/Optional.h" 2022-12-05 06:31:11 +00:00
Weining Lu 47edc70866 [LoongArch] Specify registers used for exception handling
See definition in backend D134709 and the doc [1] for more detail.

With the benefit of this change, most libcxx and libcxxabi tests pass.

[1]: https://llvm.org/docs/ExceptionHandling.html

Reviewed By: xen0n, wangleiat

Differential Revision: https://reviews.llvm.org/D139177
2022-12-05 11:42:41 +08:00
Kazu Hirata 35b4fbb559 [clang] Use std::nullopt instead of None in comments (NFC)
This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-04 15:57:24 -08:00
Krzysztof Parzyszek 0ca43d4488 DebugInfoMetadata: convert Optional to std::optional 2022-12-04 11:52:02 -06:00
serge-sans-paille 5f5b942823
Correct typo introduced in f607884a04
Fix #59321
2022-12-04 09:32:00 +01:00
Fangrui Song 2c5d49cffc [Driver] llvm::Optional => std::optional
and change a few referenced Basic and llvm/lib/WindowsDriver API
2022-12-03 20:17:05 +00:00
Kazu Hirata eeee3fee37 [Basic] Use std::nullopt instead of None (NFC)
This patch mechanically replaces None with std::nullopt where the
compiler would warn if None were deprecated.  The intent is to reduce
the amount of manual work required in migrating from Optional to
std::optional.

This is part of an effort to migrate from llvm::Optional to
std::optional:

https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-03 11:34:27 -08:00
Alex Richardson f3a17d0595 [clang] Avoid duplicating ProgramAddressSpace in TargetInfo. NFCI
This value was added to clang/Basic in D111566, but is only used during
codegen, where we can use the LLVM IR DataLayout instead. I noticed this
because the downstream CHERI targets would have to also set this value
for AArch64/RISC-V/MIPS. Instead of duplicating more information between
LLVM IR and Clang, this patch moves getTargetAddressSpace(QualType T) to
CodeGenTypes, where we can consult the DataLayout.

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D138296
2022-12-01 20:40:58 +00:00
Tomas Matheson e83f1502f1 [AArch64] Improve TargetParser API
Re-land with constexpr StringRef::substr():

The TargetParser depends heavily on a collection of macros and enums to tie
together information about architectures, CPUs and extensions. Over time this
has led to some pretty awkward API choices. For example, recently a custom
operator-- has been added to the enum, which effectively turns iteration into
a graph traversal and makes the ordering of the macro calls in the header
significant. More generally there is a lot of string <-> enum conversion
going on. I think this shows the extent to which the current data structures
are constraining us, and the need for a rethink.

Key changes:

 - Get rid of Arch enum, which is used to bind fields together. Instead of
   passing around ArchKind, use the named ArchInfo objects directly or via
   references.

 - The list of all known ArchInfo becomes an array of pointers.

 - ArchKind::operator-- is replaced with ArchInfo::implies(), which defines
   which architectures are predecessors to each other. This allows features
   from predecessor architectures to be added in a more intuitive way.

 - Free functions of the form f(ArchKind) are converted to ArchInfo::f(). Some
   functions become unnecessary and are deleted.

 - Version number and profile are added to the ArchInfo. This makes comparison
   of architectures easier and moves a couple of functions out of clang and
   into AArch64TargetParser.

 - clang::AArch64TargetInfo ArchInfo is initialised to Armv8a not INVALID.

 - AArch64::ArchProfile which is distinct from ARM::ArchProfile

 - Give things sensible names and add some comments.

Differential Revision: https://reviews.llvm.org/D138792
2022-12-01 15:30:07 +00:00
Tomas Matheson d1ef4b0a8d Revert "[AArch64] Improve TargetParser API"
Buildbots unhappy about constexpr function.

This reverts commit 450de8008b.
2022-12-01 13:06:54 +00:00
Tomas Matheson 450de8008b [AArch64] Improve TargetParser API
The TargetParser depends heavily on a collection of macros and enums to tie
together information about architectures, CPUs and extensions. Over time this
has led to some pretty awkward API choices. For example, recently a custom
operator-- has been added to the enum, which effectively turns iteration into
a graph traversal and makes the ordering of the macro calls in the header
significant. More generally there is a lot of string <-> enum conversion
going on. I think this shows the extent to which the current data structures
are constraining us, and the need for a rethink.

Key changes:

 - Get rid of Arch enum, which is used to bind fields together. Instead of
   passing around ArchKind, use the named ArchInfo objects directly or via
   references.

 - The list of all known ArchInfo becomes an array of pointers.

 - ArchKind::operator-- is replaced with ArchInfo::implies(), which defines
   which architectures are predecessors to each other. This allows features
   from predecessor architectures to be added in a more intuitive way.

 - Free functions of the form f(ArchKind) are converted to ArchInfo::f(). Some
   functions become unnecessary and are deleted.

 - Version number and profile are added to the ArchInfo. This makes comparison
   of architectures easier and moves a couple of functions out of clang and
   into AArch64TargetParser.

 - clang::AArch64TargetInfo ArchInfo is initialised to Armv8a not INVALID.

 - AArch64::ArchProfile which is distinct from ARM::ArchProfile

 - Give things sensible names and add some comments.

Differential Revision: https://reviews.llvm.org/D138792
2022-12-01 12:50:23 +00:00
Tomas Matheson f57f086714 [AArch64TargetParser] getArchFeatures -> getArchFeature
Differential Revision: https://reviews.llvm.org/D138753
2022-12-01 12:50:17 +00:00
Alex Richardson a602f76a24 [clang][TargetInfo] Use LangAS for getPointer{Width,Align}()
Mixing LLVM and Clang address spaces can result in subtle bugs, and there
is no need for this hook to use the LLVM IR level address spaces.
Most of this change is just replacing zero with LangAS::Default,
but it also allows us to remove a few calls to getTargetAddressSpace().

This also removes a stale comment+workaround in
CGDebugInfo::CreatePointerLikeType(): ASTContext::getTypeSize() does
return the expected size for ReferenceType (and handles address spaces).

Differential Revision: https://reviews.llvm.org/D138295
2022-11-30 20:24:01 +00:00
eopXD d8a27ac0e2 [NFC] Add missing period 2022-11-30 09:07:15 -08:00
Kazu Hirata eef7054f33 [Basic] Fix a warning
This patch fixes:

  clang/lib/Basic/SourceManager.cpp:1292:19: error: comparison of
  integers of different signs: 'long' and 'unsigned long'
  [-Werror,-Wsign-compare]
2022-11-30 08:57:05 -08:00
eopXD 482b8b493b [RISCV] Add macro to imply compiler availability on RISC-V Vector intrinsics version
According to version_macro.adoc under rvv-intrinsic-doc, the compiler
should have a macro to imply such availability.

Link: https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/version_macro.adoc

Reviewed By: kito-cheng, asb

Differential Revision: https://reviews.llvm.org/D138930
2022-11-30 08:35:53 -08:00
Tomas Matheson 7fea6f2e0e [AArch64] Assembly support for VMSA
Virtual Memory System Architecture (VMSA)

This is part of the 2022 A-Profile Architecture extensions and adds support for
the following:

 - Translation Hardening Extension (FEAT_THE)
 - 128-bit Page Table Descriptors (FEAT_D128)
 - 56-bit Virtual Address (FEAT_LVA3)
 - Support for 128-bit System Registers (FEAT_SYSREG128)
 - System Instructions that can take 128-bit inputs (FEAT_SYSINSTR128)
 - 128-bit Atomic Instructions (FEAT_LSE128)
 - Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE)
 - Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE)
 - Memory Attribute Index Enhancement (FEAT_AIE)

New instructions added:
 - FEAT_SYSREG128 adds MRRS and MSRR.
 - FEAT_SYSINSTR128 adds the SYSP instruction and TLBIP aliases.
 - FEAT_LSE128 adds LDCLRP, LDSET, and SWPP instructions.
 - FEAT_THE adds the set of RCW* instructions.

Specs for individual instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/

Contributors:
  Keith Walker
  Lucas Prates
  Sam Elliott
  Son Tuan Vu
  Tomas Matheson

Differential Revision: https://reviews.llvm.org/D138920
2022-11-30 13:37:02 +00:00
serge-sans-paille f607884a04
[clang] Speedup LineOffsetMapping::get
LineOffsetMapping::get is a critical function that consistently appears
in the top 5 more computation intensive functions when running the
preprocessor.

This change brings consistent speedup of ~.5% on, preprocessing time,
see

https://llvm-compile-time-tracker.com/compare.php?from=0745b0c0354a0c8e1fefb68a3876d15db6c2e27a&to=460f3f04dac025e6952d78fce104a88151508a29&stat=instructions:u

for detailed statistics.

Differential Revision: https://reviews.llvm.org/D138474
2022-11-30 14:35:53 +01:00
Alex Lorenz 60a33ded75 [clang][darwin] Use consistent version define stringifying logic for different Darwin OSes 2022-11-29 14:22:34 -08:00
Archibald Elliott 3e9b6adfc7 [ARM] Move ARM::parseBranchProtection into ARMTargetParserCommon
This should live with the Arm targets, given they have target-specific
target parsers.

Differential Revision: https://reviews.llvm.org/D137835
2022-11-25 11:33:53 +00:00
Fangrui Song 987b49395c [PPC] Undefine __ppc64__ to match GCC
GCC only defines `__ppc64__` for darwin while the darwin support has been
removed from llvm-project. The existence of `__ppc64__` makes some software
think we are compiling for big-endian PowerPC Mac; also it lures users to write
code which is not portable to GCC.

It is straightforward if a distro wants to keep the macro: add
`-D__ppc64__=1` to a Clang configuration file.

Reviewed By: thesamesam, nemanjai

Differential Revision: https://reviews.llvm.org/D137511
2022-11-22 17:01:39 -08:00
Ayke van Laethem a8efcb96e6
[AVR][Clang] Implement __AVR_HAVE_*__ macros
These macros are defined in avr-gcc and are useful when working with
assembly. For example, startup code needs to copy the contents of .data
from flash to RAM, but should use elpm (instead of lpm) on devices with
more than 64kB flash. Without __AVR_HAVE_ELPM__, there is no way to know
whether the elpm instruction is supported.

This partially fixes https://github.com/llvm/llvm-project/issues/56157.

Differential Revision: https://reviews.llvm.org/D137572
2022-11-23 01:21:09 +01:00
John Brawn 9e3264ab20 [FPEnv] Enable strict fp for AArch64 in clang
The AArch64 target now has the necessary support for strict fp, so
enable it in clang.

Differential Revision: https://reviews.llvm.org/D138143
2022-11-21 16:02:54 +00:00
Fazlay Rabbi 56c1660170 [OpenMP] Initial parsing/sema for 'strict' modifier with 'num_tasks' clause
This patch gives basic parsing and semantic analysis support for 'strict'
modifier with 'num_tasks' clause of 'taskloop' construct introduced in
OpenMP 5.1 (section 2.12.2)

Differential Revision: https://reviews.llvm.org/D138328
2022-11-18 16:26:47 -08:00
Krzysztof Parzyszek 7c476697e2 [Hexagon] Add clang flags for v71, v71t, v73 2022-11-18 09:39:47 -08:00
Fazlay Rabbi ab9eac762c [OpenMP] Initial parsing/sema for 'strict' modifier with 'grainsize' clause
This patch gives basic parsing and semantic analysis support for 'strict'
modifier with 'grainsize' clause of 'taskloop' construct introduced in
OpenMP 5.1 (section 2.12.2)

Differential Revision: https://reviews.llvm.org/D138217
2022-11-17 20:59:07 -08:00
Brad Smith 6536a67338 [Linux] Revert 1e56821bac
The glibc issue mentioned in #47994 has been fixed upstream.
2022-11-17 19:48:01 -05:00
Jennifer Yu 1e054e6b52 [OPENMP5.1] Initial support for severity clause
Differential Revision:https://reviews.llvm.org/D138227
2022-11-17 16:05:02 -08:00
Vaibhav Yenamandra 7b6fe711b2 Refactor StaticAnalyzer to use `clang::SarifDocumentWriter`
Refactor StaticAnalyzer to use clang::SarifDocumentWriter for
serializing sarif diagnostics.

Uses clang::SarifDocumentWriter to generate SARIF output in the
StaticAnalyzer.

Various bugfixes are also made to clang::SarifDocumentWriter.

Summary of changes:

clang/lib/Basic/Sarif.cpp:
  * Fix bug in adjustColumnPos introduced from prev move, it now uses
    FullSourceLoc::getDecomposedExpansionLoc which provides the correct
    location (in the presence of macros) instead of
    FullSourceLoc::getDecomposedLoc.
  * Fix createTextRegion so that it handles caret ranges correctly,
    this should bring it to parity with the previous implementation.

clang/test/Analysis/diagnostics/Inputs/expected-sarif:
  * Update the schema URL to the offical website
  * Add the emitted defaultConfiguration sections to all rules
  * Annotate results with the "level" property

clang/lib/StaticAnalyzer/Core/SarifDiagnostics.cpp:
  * Update SarifDiagnostics class to hold a clang::SarifDocumentWriter
    that it uses to convert diagnostics to SARIF.
2022-11-17 14:47:02 -05:00
Richard Smith 9e52db1827 When we run out of source locations, try to produce useful information
indicating why we ran out.
2022-11-16 14:36:16 -08:00
Ties Stuij 983f63f7f0 [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support
For both ARM and AArch64 add support for specifying -march=armv8.9a/armv9.4a to
clang. Add backend plumbing like target parser and predicate support.

For a summary of Amv8.9/Armv9.4 features, see:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022

For detailed information, consult the Arm Architecture Reference Manual for
A-profile architecture:
https://developer.arm.com/documentation/ddi0487/latest/

People who contributed to this patch:
- Keith Walker
- Ties Stuij

Reviewed By: tmatheson

Differential Revision: https://reviews.llvm.org/D138010
2022-11-16 10:20:14 +00:00
Jennifer Yu 628fdc3f57 [OPENMP]Initial support for at clause
Error directive is allowed in both declared and executable contexts.
The function ActOnOpenMPAtClause is called in both places during the
parsers.

Adding a param "bool InExContext" to identify context which is used to
emit error massage.

Differential Revision: https://reviews.llvm.org/D137851
2022-11-15 14:06:50 -08:00
Fangrui Song ea5be2571d [AVR] Fix use-of-uninitialized-value after D137520 2022-11-15 11:06:18 -08:00
Ayke van Laethem 09ab9d4d11
[AVR][Clang] Implement __AVR_ARCH__ macro
This macro is defined in avr-gcc, and is very useful especially in
assembly code to check whether particular instructions are supported. It
is also the basis for other macros like __AVR_HAVE_ELPM__.

Differential Revision: https://reviews.llvm.org/D137521
2022-11-15 15:29:37 +01:00
Ayke van Laethem d2563775cd
[AVR][Clang] Move family names into MCU list
This simplifies the code by avoiding some special cases for family names
(as opposed to device names).

Differential Revision: https://reviews.llvm.org/D137520
2022-11-15 15:29:37 +01:00
Chuanqi Xu cb2289f392 [C++20] [Modules] Attach implicitly declared allocation funcitons to
global module fragment

[basic.stc.dynamic.general]p2 says:
> The library provides default definitions for the global allocation
> and deallocation functions. Some global allocation and
> deallocation
> functions are replaceable ([new.delete]); these are attached to
> the global module ([module.unit]).

But we didn't take this before and the implicitly generated functions
will live in the module purview if we're compiling a module unit. This
is bad since the owning module will affect the linkage of the
declarations. This patch addresses this.

Closes https://github.com/llvm/llvm-project/issues/58560
2022-11-15 17:21:48 +08:00