Commit Graph

3 Commits

Author SHA1 Message Date
Craig Topper b6ad7ab89e [RISCV] Prevent autovectorization using vscale with Zvl32b.
RVVBitsPerBlock is 64. If VLen==32, VLen/RVVBitsPerBlock is 0.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D137280
2022-11-02 13:55:21 -07:00
Philip Reames 9a8f3b113d [clang][RISCV] Set vscale_range attribute based on VLEN
Follow up on D135894, restructure code to work in terms of minimum and maximum VLEN coming from RISCVISAInfo.cpp. In the original review, I'd mentioned that MinVLEN was sometimes zero. This turns out to be a case of human error, combined with really bad (lack of) error reporting.

This patch adds appropriate tests for various vector extension combinations to show the mechanism works, but doesn't try to provide exhaustive coverage of the extension interactions. Presumably, that is already covered in existing tests elsewhere.

Differential Revision: https://reviews.llvm.org/D136106
2022-10-19 16:14:33 -07:00
Philip Reames 4467c781d7 [clang][RISCV] Set vscale_range attribute based on presence of "v" extension
This follows the path that AArch64 SVE has taken. Doing this via a function attribute set in the frontend is basically a workaround for the fact that several analyzes which need the information (i.e. known bits, lvi, scev) can't easily use TTI without significant amounts of plumbing changes.

This patch hard codes "v" numbers, and directly follows the SVE precedent as a result. In a follow up, I hope to drive this from RISCVISAInfo.h/cpp instead, but the MinVLen number being returned from that interface seemed to always be 0 (which is wrong), and I haven't figured out what's going wrong there.

Differential Revision: https://reviews.llvm.org/D135894
2022-10-17 11:33:03 -07:00