Commit Graph

2 Commits

Author SHA1 Message Date
Sheng 28e850a8da [TableGen] Add support for variable length instruction in decoder generator
To support variable length instructions, I think of them as fixed length instructions with the "maximum length". For example, if there're three instructions with 2, 6 and 9 bytes, we can fit them into the algorithm by treating them all as 9 bytes.

Also, since we can't know the length of the instruction in advance, there is a function object with type `void(APInt &, uint64_t)` added in the parameter list of `decodeInstruction` and `fieldFromInstruction`. We can use this to supply the additional bits the decoder needs after we know the opcode of the instruction.

Finally, `InstrLenTable` is added to let the decoder know the length of the instructions.

See D120960 for its usage.

Reviewed By: myhsu

Differential Revision: https://reviews.llvm.org/D120958
2022-05-03 03:37:13 +08:00
Min-Yih Hsu 31f9519d48 [TableGen][CodeEmitter] Introducing the VarLenCodeEmitterGen infrastructure
Full write up:
https://gist.github.com/mshockwave/66e98d099256deefc062633909bb7b5b

The existing CodeEmitterGen infrastructure is unable to generate encoder
function for ISAs with variable-length instructions. This patch
introduces a new infrastructure to support variable-length instruction
encoding, including a new TableGen syntax for writing instruction
encoding directives and a new TableGen backend component,
VarLenCodeEmitterGen, built on top of CodeEmitterGen.

Differential Revision: https://reviews.llvm.org/D115128
2022-02-11 09:31:11 -08:00