Andrew V. Tischenko
|
75745d0c3e
|
This patch closes PR#32216: Better testing of schedule model instruction latencies/throughputs.
The details are here: https://reviews.llvm.org/D30941
llvm-svn: 300311
|
2017-04-14 07:44:23 +00:00 |
|
Simon Pilgrim
|
a3362a1c9e
|
[X86][SSE] Added chained FDIV test cases for D26855
Tests to demonstrate throughput-latency decision between div and rcp on faster hardware such as Haswell
llvm-svn: 294750
|
2017-02-10 14:56:12 +00:00 |
|
Simon Pilgrim
|
05ac1f70be
|
[X86][SSE] Added extra FMA/NO-FMA reciprocal test cases for D26855
Test for expected codegen for nr reciprocal cases with/without FMA
llvm-svn: 294587
|
2017-02-09 14:14:06 +00:00 |
|
Simon Pilgrim
|
361f8d7869
|
[X86][SSE] Add target cpu specific reciprocal tests
As discussed on D26855, check individual cpu targets as part of the investigation into moving more combines to MachineCombiner
llvm-svn: 294128
|
2017-02-05 18:26:17 +00:00 |
|
Andrew V. Tischenko
|
5f643ad847
|
Extra coverage tests to demonstrate fixes in D72618 and D26855
llvm-svn: 289931
|
2016-12-16 09:56:02 +00:00 |
|
Alexey Bataev
|
2db6045b29
|
Revert "[TESTS] Initial commit of tests, by Andrew Tischenko"
This reverts commit ee709f8988653a0334fbf100cdbbdd83a3933347.
llvm-svn: 289814
|
2016-12-15 12:26:18 +00:00 |
|
Alexey Bataev
|
67c90c7d95
|
[TESTS] Initial commit of tests, by Andrew Tischenko
llvm-svn: 289807
|
2016-12-15 11:48:24 +00:00 |