13e8a85820
HexagonISelLowering.cpp: fix 'enum in bool context' warning
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llvm-svn: 327832
2018-03-19 12:55:58 +00:00
9915291ab8
[Hexagon] Fix zero-extending non-HVX bool vectors
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llvm-svn: 327712
2018-03-16 15:03:37 +00:00
480ab2bbc4
[Hexagon] Ignore indexed loads when handling unaligned loads
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llvm-svn: 327037
2018-03-08 18:15:13 +00:00
2c3edf0567
[Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned ones
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This is a follow-up to r325169, this time for all types, not just HVX
vector types.
Disable this by default, since it's not always safe.
llvm-svn: 326915
2018-03-07 17:27:18 +00:00
f608812bde
[Hexagon] Handle VACOPY in isel lowering
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llvm-svn: 326599
2018-03-02 18:35:57 +00:00
e0d7de7d7b
Recommit [Hexagon] Make the vararg handling a bit more robust
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Use the FunctionType of the callee when it's available. It may not be
available for synthetic calls to functions specified by external symbols.
llvm-svn: 325269
2018-02-15 17:20:07 +00:00
8a9eff6b87
Revert "[Hexagon] Make the vararg handling a bit more robust"
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This is breaking lit tests.
llvm-svn: 325266
2018-02-15 16:57:44 +00:00
568107275d
[Hexagon] Make the vararg handling a bit more robust
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The FunctionType of the callee is always available, even if the Function
of the callee is not. Use that to get the number of fixed parameters.
llvm-svn: 325259
2018-02-15 16:24:30 +00:00
18e0d2a1f8
[Hexagon] Fix lowering of formal arguments after r324737
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Lowering of formal arguments needs to be aware of vararg functions.
llvm-svn: 325255
2018-02-15 15:47:53 +00:00
ad83ce4cb4
[Hexagon] Split HVX vector pair loads/stores, expand unaligned loads
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llvm-svn: 325169
2018-02-14 20:46:06 +00:00
cfbe6ba20c
[Hexagon] Simplify some code, NFC
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llvm-svn: 325014
2018-02-13 15:35:07 +00:00
080bf219c2
[Hexagon] Remove unnecessary check
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llvm-svn: 325013
2018-02-13 15:34:29 +00:00
7cfe7cbccc
[Hexagon] Express calling conventions via .td file instead of hand-coding
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Additionally, simplify the rest of the argument/parameter lowering code.
llvm-svn: 324737
2018-02-09 15:30:02 +00:00
8abaf8954a
[Hexagon] Extract HVX lowering and selection into HVX-specific files, NFC
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llvm-svn: 324392
2018-02-06 20:22:20 +00:00
97a5095db6
[Hexagon] Lower concat of more than 2 vectors into build_vector
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llvm-svn: 324391
2018-02-06 20:18:58 +00:00
88f11003a0
[Hexagon] Split HVX operations on vector pairs
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Vector pairs are legal types, but not every operation can work on pairs.
For those operations that are legal for single vectors, generate a concat
of their results on pair halves.
llvm-svn: 324350
2018-02-06 14:24:57 +00:00
69f1d7e370
[Hexagon] Handle lowering of SETCC via setCondCodeAction
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It was expanded directly into instructions earlier. That was to avoid
loads from a constant pool for a vector negation: "xor x, splat(i1 -1)".
Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of
all true and all false values, and handle setcc with negations through
selection patterns.
llvm-svn: 324348
2018-02-06 14:16:52 +00:00
15efa98f63
[Hexagon] Rename HexagonISelLowering::getNode to getInstr, NFC
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llvm-svn: 323916
2018-01-31 21:17:03 +00:00
1108ee2496
[Hexagon] Implement HVX codegen for vector shifts
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llvm-svn: 323914
2018-01-31 20:49:24 +00:00
9eb085e6cf
[Hexagon] Handle ANY_EXTEND_VECTOR_INREG in lowering
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llvm-svn: 323912
2018-01-31 20:48:11 +00:00
b843f75179
[Hexagon] Handle SETCC on vector pairs in lowering
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llvm-svn: 323911
2018-01-31 20:46:55 +00:00
96a284114e
Revert: [Hexagon] Make sure that offset on globals matches alignment requirements
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This reverts r323562, since it wasn't actually necessary. Constant-
extended offsets do not need to be aligned, as long as the effective
address is aligned.
Keep the testcase, with a modification which checks that such offsets
are not unnecessarily avoided.
llvm-svn: 323798
2018-01-30 18:10:27 +00:00
d4273abb69
[Hexagon] Make sure that offset on globals matches alignment requirements
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A correctly aligned address may happen to be separated into a variable
part and a constant part, where the constant part does not match the
alignment needed in a load/store that uses this address. Such a constant
cannot be used as an immediate offset in an indexed instruction.
When lowering a global address, make sure that if there is an offset
folded into the global, the offset is valid for all uses in load/store
instructions.
llvm-svn: 323562
2018-01-26 21:20:04 +00:00
b2c458e648
[Hexagon] SETEQ and SETNE are valid integer condition codes
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llvm-svn: 323452
2018-01-25 18:07:27 +00:00
5aef4b5997
[Hexagon] Remove unused HexagonISD opcodes, NFC
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llvm-svn: 323324
2018-01-24 14:07:37 +00:00
c1e2290d37
Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.
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llvm-svn: 323258
2018-01-23 21:22:16 +00:00
3780a0e1fa
[Hexagon] Implement basic vector operations on vectors vNi1
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In addition to that, make sure that there are no boolean vector types that
are associated with multiple register classes. Specifically, remove v32i1
and v64i1 from integer register classes. These types will correspond to
results of vector comparisons, and as such should belong to the vector
predicate class. Having them in scalar registers as well makes legalization
ambiguous.
llvm-svn: 323229
2018-01-23 17:53:59 +00:00
7fb738ab71
[Hexagon] Implement signed and unsigned multiply-high for vectors
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llvm-svn: 322499
2018-01-15 18:43:55 +00:00
b8f2a1e7b7
[Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectors
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The old implementation was not always correct. The new one recognizes
more shuffles that match specific instructions.
llvm-svn: 322498
2018-01-15 18:33:33 +00:00
240df6faa4
[Hexagon] Fix building 64-bit vector from constant values
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The constants were aggregated in a reverse order.
llvm-svn: 322303
2018-01-11 18:30:41 +00:00
4ef6cfff6a
[Hexagon] Cast elements to correct type when creating constant vector
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llvm-svn: 322301
2018-01-11 18:03:23 +00:00
b3e50ac1c4
[Hexagon] Set boolean contents in HexagonISelLowering
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llvm-svn: 321891
2018-01-05 20:41:50 +00:00
b1b2960336
[Hexagon] Replace INSERTRP/EXTRACTRP with INSERT/EXTRACT in HexagonISD
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llvm-svn: 321798
2018-01-04 13:56:04 +00:00
e4ce92cabf
[Hexagon] Allow construction of HVX vector predicates
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Handle BUILD_VECTOR of boolean values.
llvm-svn: 321220
2017-12-20 20:49:43 +00:00
fb0fcacb9d
[Hexagon] Legalize vector elements to i32 in buildVector32/64
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llvm-svn: 321218
2017-12-20 20:33:49 +00:00
8f6b0c850a
[Hexagon] Adjust the value type for BCvt in LowerFormalArguments
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llvm-svn: 321177
2017-12-20 14:44:05 +00:00
7259263790
i[Hexagon] ANY_EXTEND_VECTOR_INREG should be Custom, not Legal in r321004
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llvm-svn: 321005
2017-12-18 18:41:52 +00:00
6b589e593d
[Hexagon] Generate HVX code for vector sign-, zero- and any-extends
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Implement any-extend as zero-extend.
llvm-svn: 321004
2017-12-18 18:32:27 +00:00
5439a70d97
[Hexagon] Prefer to widen HVX vectors instead of promoting
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llvm-svn: 321002
2017-12-18 18:21:01 +00:00
f1caa2833f
MachineFunction: Return reference from getFunction(); NFC
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The Function can never be nullptr so we can return a reference.
llvm-svn: 320884
2017-12-15 22:22:58 +00:00
7d7adf4f2e
TLI: Allow using PSV for intrinsic mem operands
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llvm-svn: 320756
2017-12-14 22:34:10 +00:00
1117133687
DAG: Expose all MMO flags in getTgtMemIntrinsic
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Rather than adding more bits to express every
MMO flag you could want, just directly use the
MMO flags. Also fixes using a bunch of bool arguments to
getMemIntrinsicNode.
On AMDGPU, buffer and image intrinsics should always
have MODereferencable set, but currently there is no
way to do that directly during the initial intrinsic
lowering.
llvm-svn: 320746
2017-12-14 21:39:51 +00:00
470760533a
[Hexagon] Generate HVX code for comparisons and selects
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llvm-svn: 320744
2017-12-14 21:28:48 +00:00
708c9f5947
[Hexagon] Remove vectors of i64 from valid HVX types
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HVX does not support operations on 64-bit integers.
llvm-svn: 320722
2017-12-14 18:35:24 +00:00
a8ab1b75cb
[Hexagon] Add support for Hexagon V65
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llvm-svn: 320404
2017-12-11 18:57:54 +00:00
039d4d9286
[Hexagon] Generate HVX code for basic arithmetic operations
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Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32.
llvm-svn: 320063
2017-12-07 17:37:28 +00:00
7d37dd8902
[Hexagon] Generate HVX code for vector construction and access
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Support for:
- build vector,
- extract vector element, subvector,
- insert vector element, subvector,
- shuffle.
llvm-svn: 319901
2017-12-06 16:40:37 +00:00
f4dcc42e7b
[Hexagon] Remove HexagonISD::PACKHL
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llvm-svn: 319352
2017-11-29 19:59:29 +00:00
6a8e5f4b0f
[Hexagon] Create helpers extractVector and insertVector in lowering
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llvm-svn: 319351
2017-11-29 19:58:10 +00:00
081e458e90
[Hexagon] Make sure to zero-extend bytes before building a vector
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llvm-svn: 319204
2017-11-28 19:13:17 +00:00
Hans Wennborg