Commit Graph

5692 Commits

Author SHA1 Message Date
Jim Grosbach ef70e9b704 ARM allows '' syntax, not just '#imm' for assembly.
Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.

llvm-svn: 146285
2011-12-09 22:25:03 +00:00
Jim Grosbach 6192b6570d ARM assembly aliases for BIC<-->AND (immediate).
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057

llvm-svn: 146283
2011-12-09 22:02:17 +00:00
Jim Grosbach ea1b353e67 ARM NEON data type aliases for VBIC(register).
llvm-svn: 146281
2011-12-09 21:46:04 +00:00
Jim Grosbach d146a02c79 ARM assembly parsing and encoding for VLD2 with writeback.
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.

llvm-svn: 146278
2011-12-09 21:28:25 +00:00
Jakob Stoklund Olesen f85723626c User a helper overload for a common pattern.
llvm-svn: 146270
2011-12-09 19:44:39 +00:00
Jim Grosbach 8a4009dab2 Tidy up. Better base class factoring.
llvm-svn: 146267
2011-12-09 19:07:20 +00:00
Jim Grosbach b076e6f3d5 Tidy up. Better base class factoring.
llvm-svn: 146266
2011-12-09 18:54:11 +00:00
Jakob Stoklund Olesen 5f5fa12413 Tweak debugging output.
llvm-svn: 146264
2011-12-09 18:20:35 +00:00
Jim Grosbach 8cc83fa1b7 ARM convenience aliases for VSQRT.
llvm-svn: 146201
2011-12-08 22:51:25 +00:00
Jim Grosbach db731be7b8 ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
llvm-svn: 146194
2011-12-08 22:19:04 +00:00
Jim Grosbach ba7d6ed05d ARM VSHR implied destination operand form aliases.
llvm-svn: 146192
2011-12-08 22:06:06 +00:00
Jim Grosbach 98bc797b4d ARM asm parser, just issue a warning for a duplicate reg in a list.
For better 'gas' compatibility.

llvm-svn: 146185
2011-12-08 21:34:20 +00:00
Jim Grosbach ab9c8bb45b ARM VSUB implied destination operand form aliases.
llvm-svn: 146182
2011-12-08 20:56:26 +00:00
Jim Grosbach 66c9ad7642 ARM VQADD implied destination operand form aliases.
llvm-svn: 146179
2011-12-08 20:49:43 +00:00
Jim Grosbach e9ee1092e1 ARM a few more VMUL implied destination operand form aliases.
llvm-svn: 146177
2011-12-08 20:42:35 +00:00
Jim Grosbach 4edc7360c7 ARM assembler support for register name aliases.
rdar://10550084

llvm-svn: 146170
2011-12-08 19:27:38 +00:00
Daniel Dunbar c09e4593b2 Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.

llvm-svn: 146157
2011-12-08 17:32:18 +00:00
Stepan Dyatkovskiy a4bcf27dae Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
llvm-svn: 146143
2011-12-08 07:55:03 +00:00
Jim Grosbach 00326406d4 ARM NEON two-operand aliases for VSHL(immediate).
llvm-svn: 146125
2011-12-08 01:30:04 +00:00
Jakob Stoklund Olesen 14e024dff7 Drop the HasInlineAsm flag.
It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.

A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.

llvm-svn: 146124
2011-12-08 01:22:39 +00:00
Jim Grosbach f10a635eb4 ARM NEON two-operand aliases for VSHL(register).
llvm-svn: 146123
2011-12-08 01:12:35 +00:00
Jakob Stoklund Olesen bd97f5d753 Simplify offset verification.
llvm-svn: 146121
2011-12-08 01:10:05 +00:00
Jim Grosbach 0dd1bc9c79 Fix copy/past-o.
llvm-svn: 146120
2011-12-08 01:02:26 +00:00
Jim Grosbach 31a462c02c ARM NEON two-operand aliases for VMUL.
llvm-svn: 146119
2011-12-08 00:59:47 +00:00
Jakob Stoklund Olesen 2a82333f54 Don't include alignment padding in BBInfo.Size.
Compute alignment padding before and after basic blocks dynamically.

Heed basic block alignment.

This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size.  It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.

This makes the ARMConstantIslandPass aware of aligned basic blocks.

It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size.  If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected.  This could cause constant
pool entries to move out of range.

To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly.  Normal
functions should be unaffected.

llvm-svn: 146118
2011-12-08 00:55:02 +00:00
Jim Grosbach 9a6ba3c94e ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
llvm-svn: 146116
2011-12-08 00:52:55 +00:00
Jim Grosbach 086d013e56 ARM VFP support 'flds/fldd' aliases for 'vldr'
llvm-svn: 146115
2011-12-08 00:49:29 +00:00
Jim Grosbach 6600f520b0 ARM optional destination operand variants for VEXT instructions.
llvm-svn: 146114
2011-12-08 00:43:47 +00:00
Jim Grosbach 3050625a50 ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
llvm-svn: 146111
2011-12-08 00:31:07 +00:00
Jim Grosbach 3b559ff3c5 ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
For 'gas' compatibility.

llvm-svn: 146106
2011-12-07 23:40:58 +00:00
Jim Grosbach 90d961250b ARM two-operand aliases for VAND/VEOR/VORR instructions.
llvm-svn: 146095
2011-12-07 23:08:12 +00:00
Jim Grosbach 3744a7febb ARM two-operand aliases for VADDW instructions.
llvm-svn: 146093
2011-12-07 23:01:10 +00:00
Jim Grosbach 552691556c ARM two-operand aliases for VADD instructions.
llvm-svn: 146091
2011-12-07 22:52:54 +00:00
Jim Grosbach d633c2f120 Nuke inadvertant debugging commit.
llvm-svn: 146057
2011-12-07 19:56:16 +00:00
Jim Grosbach d6ae4ba002 Darwin assembler improved relocs when w/o subsections_via_symbols.
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.

llvm-svn: 146054
2011-12-07 19:46:59 +00:00
Jim Grosbach 18b0e5dca0 Thumb2 alias for long-form pop and friends.
rdar://10542474

llvm-svn: 146046
2011-12-07 18:32:28 +00:00
Jim Grosbach 7f882399b8 ARM support the .arm and .thumb directives for assembly mode switching.
llvm-svn: 146042
2011-12-07 18:04:19 +00:00
Jim Grosbach 721042fa3a ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
llvm-svn: 146039
2011-12-07 17:51:15 +00:00
Evan Cheng 7f8e563a69 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Jakob Stoklund Olesen 2f0400b780 Eliminate delta argument from AdjustBBOffsetsAfter.
The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.

Eliminate one redundant AdjustBBOffsetsAfter call.

llvm-svn: 146018
2011-12-07 05:17:30 +00:00
Jakob Stoklund Olesen 97c857199e Compute some alignment information for each basic block.
These fields are not used for anything yet.

llvm-svn: 146017
2011-12-07 04:17:35 +00:00
Jim Grosbach 2cf294a213 ARM tidy up and remove no longer needed InstAlias definitions.
The TokenAlias handling of data type suffices renders these unnecessary.

llvm-svn: 146010
2011-12-07 01:50:36 +00:00
Jakob Stoklund Olesen af748e1180 Move common expression into a method.
llvm-svn: 146008
2011-12-07 01:22:52 +00:00
Jim Grosbach 585ce30b8b ARM Implement ARM ARM Table A7-3 via TokenAlias.
Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.

rdar://10435076

llvm-svn: 146007
2011-12-07 01:17:58 +00:00
Jakob Stoklund Olesen e2b3ff2a07 Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>.
No functional change is intended.

llvm-svn: 146005
2011-12-07 01:08:25 +00:00
Jim Grosbach d4b8249434 ARM: NEON SHLL instruction immediate operand range checking.
llvm-svn: 146003
2011-12-07 01:07:24 +00:00
Jim Grosbach 47c24c2084 ARM: Parameterize the immediate operand type for NEON VSHLL.
No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.

llvm-svn: 145994
2011-12-07 00:02:17 +00:00
Jakob Stoklund Olesen cc6bfa8e79 Revert r145971: "Use conservative size estimate for tBR_JTr."
This caused more offset errors.

llvm-svn: 145980
2011-12-06 22:41:31 +00:00
Evan Cheng 2a81dd4a3c First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975
2011-12-06 22:12:01 +00:00
Jakob Stoklund Olesen 33fe130e12 Use conservative size estimate for tBR_JTr.
This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.

It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.

llvm-svn: 145971
2011-12-06 21:55:39 +00:00