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279 Commits

Author SHA1 Message Date
Akira Hatanaka 5ee8464e48 Rename WrapperPIC. It is now used for both pic and static. 
llvm-svn: 146232
 2011-12-09 01:53:17 +00:00
Akira Hatanaka 8e16aac534 jalr should use t9 ($25) for indirect calls regardless of the relocation model 
specified.

llvm-svn: 146229
 2011-12-09 01:45:12 +00:00
Akira Hatanaka f10ee84956 Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo in 
MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have
call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the
target is Mips64.

llvm-svn: 146183
 2011-12-08 21:05:38 +00:00
Akira Hatanaka dee6c8275c Implement 64-bit support for thread local storage handling. 
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC. 
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
  substituted with other existing nodes.

llvm-svn: 146175
 2011-12-08 20:34:32 +00:00
Akira Hatanaka c5b5a8d8b1 Modify LowerFCOPYSIGN to handle Mips64. 
llvm-svn: 146080
 2011-12-07 21:48:50 +00:00
Bruno Cardoso Lopes 61e6d987bf Add a few moreLocal/Global R_MIPS_GOT related fixups and 
make the addend fixup code a bit more generic

Patch by Jack Carter.

llvm-svn: 145998
 2011-12-07 00:28:57 +00:00
Akira Hatanaka 20cee2eba1 Add definitions of 64-bit extract and insert instrucions and make 
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.

llvm-svn: 145853
 2011-12-05 21:26:34 +00:00
Akira Hatanaka 34e3df76f9 Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and 
O32 with relocation-model=pic too.

llvm-svn: 145850
 2011-12-05 21:03:03 +00:00
Akira Hatanaka b31abde0f3 Lower 64-bit constant pool node. 
llvm-svn: 144849
 2011-11-16 22:44:38 +00:00
Akira Hatanaka eb42071721 Lower 64-bit block address. 
llvm-svn: 144847
 2011-11-16 22:42:10 +00:00
Akira Hatanaka 66a14c0650 Simplify function PassByValArg64. 
llvm-svn: 144664
 2011-11-15 18:42:25 +00:00
Benjamin Kramer 319904cc7e Unbreak Release builds. 
llvm-svn: 144560
 2011-11-14 19:51:48 +00:00
Akira Hatanaka 0b8bc00424 AnalyzeCallOperands function for N32/64. 
N32/64 places all variable arguments in integer registers (or on stack),
regardless of their types, but follows calling convention of non-vaarg function
when it handles fixed arguments.

llvm-svn: 144553
 2011-11-14 19:02:54 +00:00
Akira Hatanaka 52359363f2 Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64. 
llvm-svn: 144552
 2011-11-14 19:01:09 +00:00
Akira Hatanaka d673cfe027 Remove variable that keeps the size of area used to save byval or variable 
argument registers on the callee's stack frame, along with functions that set
and get it.
    
It is not necessary to add the size of this area when computing stack size in
emitPrologue, since it has already been accounted for in
PEI::calculateFrameObjectOffsets.

llvm-svn: 144549
 2011-11-14 18:56:20 +00:00
Akira Hatanaka 77733535eb Fix typo. 
llvm-svn: 144453
 2011-11-12 02:38:12 +00:00
Akira Hatanaka 19891f843c Implement Mips64's handling of byval arguments in LowerCall. 
llvm-svn: 144452
 2011-11-12 02:34:50 +00:00
Akira Hatanaka fb9bae34da Implement Mips64's handling of byval arguments in LowerFormalArguments. 
llvm-svn: 144449
 2011-11-12 02:29:58 +00:00
Akira Hatanaka 202f6400ef Function for handling byval arguments. 
llvm-svn: 144447
 2011-11-12 02:20:46 +00:00
Bruno Cardoso Lopes c85e3ff334 Mips MC object code emission improvements: 
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter

llvm-svn: 144414
 2011-11-11 22:58:42 +00:00
Akira Hatanaka 4a63d1c0f0 Do not try to detect DAG combine patterns for integer multiply-add/sub if value 
type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.

llvm-svn: 144373
 2011-11-11 04:18:21 +00:00
Akira Hatanaka 21cbc25bbb 64-bit atomic instructions. 
llvm-svn: 144372
 2011-11-11 04:14:30 +00:00
Akira Hatanaka 9189d7127f Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64. 
llvm-svn: 144371
 2011-11-11 04:11:56 +00:00
Akira Hatanaka 4bdfec57ba Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC. 
llvm-svn: 144370
 2011-11-11 04:06:38 +00:00
Pete Cooper 82cd9e81fc Added invariant field to the DAG.getLoad method and changed all calls. 
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses

llvm-svn: 144100
 2011-11-08 18:42:53 +00:00
Akira Hatanaka 104b7e3f2c Make changes necessary in LowerFormalArguments to support Mips64. 
llvm-svn: 143218
 2011-10-28 19:55:48 +00:00
Akira Hatanaka b20a325baf Make changes necessary in LowerCall to support Mips64. 
llvm-svn: 143217
 2011-10-28 19:49:00 +00:00
Akira Hatanaka 7989f15d37 Add variable IsO32 to MipsTargetLowering. 
llvm-svn: 143213
 2011-10-28 18:47:24 +00:00
Eli Friedman 4c42be5b32 Fix misc warnings. Patch by Joe Abbey. 
llvm-svn: 142332
 2011-10-18 03:17:34 +00:00
Akira Hatanaka a7e0b90897 Add definitions of conditional moves with 64-bit operands. Comment out code for 
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 

llvm-svn: 142226
 2011-10-17 18:53:29 +00:00
Akira Hatanaka 09b23eb7bc Modify lowering of GlobalAddress so that correct code is emitted when target is 
Mips64.

llvm-svn: 141618
 2011-10-11 00:55:05 +00:00
Akira Hatanaka be68f3c348 Add definitions of 64-bit loads and stores. Add a patterns for unaligned 
zextloadi32 for which there is no corresponding pseudo or real instruction. 

llvm-svn: 141608
 2011-10-11 00:27:28 +00:00
Akira Hatanaka b1538f91dc Add support for 64-bit divide instructions. 
llvm-svn: 141024
 2011-10-03 21:06:13 +00:00
Akira Hatanaka 7ba8a8d656 Add definitions of Mips64 rotate instructions. 
llvm-svn: 140870
 2011-09-30 18:51:46 +00:00
Akira Hatanaka a6a9c20c23 Set register class of a register according to value of HasMips64. 
llvm-svn: 140570
 2011-09-26 21:55:17 +00:00
Akira Hatanaka 7b502920ef Define variable HasMips64 in MipsTargetLowering. 
llvm-svn: 140569
 2011-09-26 21:47:02 +00:00
Akira Hatanaka e5ce709022 In single float mode, double precision FP arguments are passed in integer 
registers, so there is no need to check here.

llvm-svn: 140568
 2011-09-26 21:37:50 +00:00
Akira Hatanaka e96273e75d Preparation for adding simple Mips64 instructions. 
llvm-svn: 140443
 2011-09-24 01:34:44 +00:00
Akira Hatanaka ceb55e72de Make FGR64RegisterClass available if target is Mips64. 
llvm-svn: 140397
 2011-09-23 18:28:39 +00:00
Akira Hatanaka 61bbcce84a Do not rely on the enum values of argument registers A0-A3 being consecutive. 
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.

llvm-svn: 140363
 2011-09-23 00:58:33 +00:00
Akira Hatanaka 6a5f8b2fd4 Remove unnecessary condition check. 
llvm-svn: 140291
 2011-09-22 02:41:29 +00:00
Akira Hatanaka bb49e721b8 Change the names of functions isMips* to hasMips*. 
llvm-svn: 140214
 2011-09-20 23:53:09 +00:00
Akira Hatanaka 79738336a8 Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't 
yet legal according to comments in LegalizeDAG.cpp:227. 

Memcpy nodes created for copying byval arguments are inserted before
CALLSEQ_START.

The two failing tests reported in PR10876 pass after applying this patch.  

llvm-svn: 140046
 2011-09-19 20:26:02 +00:00
Duncan Sands f2641e1bc1 Add codegen support for vector select (in the IR this means a select 
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.

llvm-svn: 139159
 2011-09-06 19:07:46 +00:00
Eli Friedman 7dfa791f4f Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly. 
llvm-svn: 138751
 2011-08-29 18:23:02 +00:00
Akira Hatanaka 419fd4f315 Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not 
needed for Mips32.

llvm-svn: 138132
 2011-08-19 22:59:00 +00:00
Akira Hatanaka fb4161ae88 Use subword loads instead of a 4-byte load when the size of a structure (or a 
piece of it) that is being passed by value is smaller than a word.

llvm-svn: 138007
 2011-08-18 23:39:37 +00:00
Akira Hatanaka 73d78b7ab1 Make IsShiftedMask a static function rather than defining it in an 
anonymous namespace.

llvm-svn: 137975
 2011-08-18 20:07:42 +00:00
Akira Hatanaka eea541ce4e Changed definition of EXT and INS per Bruno's comments. 
llvm-svn: 137892
 2011-08-17 22:59:46 +00:00
Akira Hatanaka b2e7558c40 Add support for half-word unaligned loads and stores. 
llvm-svn: 137848
 2011-08-17 18:49:18 +00:00