OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity
118,433 Commits 31 Branches 0 Tags 2.2 GiB
Commit Graph

206 Commits

Author SHA1 Message Date
Nick Lewycky 50f02cb21b Move global variables in TargetMachine into new TargetOptions class. As an API 
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

llvm-svn: 145714
 2011-12-02 22:16:29 +00:00
Jan Sjödin 1280eb1d06 Add XOP feature flag. 
llvm-svn: 145682
 2011-12-02 15:14:37 +00:00
Craig Topper 228d9131aa Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. 
llvm-svn: 143319
 2011-10-30 19:57:21 +00:00
David Meyer 49045ddb4c Remove NaClMode 
llvm-svn: 142338
 2011-10-18 05:29:23 +00:00
Craig Topper e20793a4f1 Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147. 
llvm-svn: 142177
 2011-10-17 05:33:10 +00:00
Craig Topper aea148c366 Add X86 BZHI instruction as well as BMI2 feature detection. 
llvm-svn: 142122
 2011-10-16 07:55:05 +00:00
Craig Topper 6c8879e3ab Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7. 
llvm-svn: 142089
 2011-10-16 00:21:51 +00:00
Craig Topper 3657fe4b17 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
llvm-svn: 141939
 2011-10-14 03:21:46 +00:00
Craig Topper 271064e873 Add X86 LZCNT instruction. Including instruction selection support. 
llvm-svn: 141651
 2011-10-11 06:44:02 +00:00
Craig Topper a14c5723eb Put a bunch of calls to ToggleFeature behind proper if statements. 
llvm-svn: 141527
 2011-10-10 05:34:02 +00:00
Craig Topper fe9179fa4f Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. 
llvm-svn: 141505
 2011-10-09 07:31:39 +00:00
Craig Topper 786bdb9e14 Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. 
llvm-svn: 141007
 2011-10-03 17:28:23 +00:00
Rafael Espindola 6559656e73 Detect attempt to use segmented stacks on non ELF systems and error 
(not assert) early.

llvm-svn: 139233
 2011-09-07 16:10:57 +00:00
Nick Lewycky 73df7e3830 Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain 
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!

llvm-svn: 139125
 2011-09-05 21:51:43 +00:00
Eli Friedman 5e5704277f Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction. 
llvm-svn: 138660
 2011-08-26 21:21:21 +00:00
Evan Cheng bc153d49b7 Next round of MC refactoring. This patch factor MC table instantiations, MC 
registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184
 2011-07-14 20:59:42 +00:00
Evan Cheng c5e6d2f519 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo 
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884
 2011-07-11 03:57:24 +00:00
Eli Friedman fe2088bb1f Really force on 64bit for 64-bit targets. Should fix remaining failures on unknown x86/non-x86 targets. 
llvm-svn: 134773
 2011-07-08 23:43:01 +00:00
Eli Friedman 5286833f4a Revert earlier unnecessary hack. Make sure we correctly force on 64bit and cmov for 64-bit targets. 
llvm-svn: 134768
 2011-07-08 23:07:42 +00:00
Evan Cheng 60fc0fca5c Restore old behavior. Always auto-detect features unless cpu or features are specified. 
llvm-svn: 134757
 2011-07-08 22:30:25 +00:00
Eli Friedman e2f76c4ade Default 64-bit target features and SSE2 on when a triple specifies x86-64. Clean up all the other hacks which are now unnecessary. 
llvm-svn: 134753
 2011-07-08 22:16:47 +00:00
Evan Cheng 964cb5feb0 For non-x86 host, used generic as CPU name. 
llvm-svn: 134741
 2011-07-08 21:14:14 +00:00
Evan Cheng 4d1ca96bfc Eliminate asm parser's dependency on TargetMachine: 
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".

llvm-svn: 134678
 2011-07-08 01:53:10 +00:00
Evan Cheng 13bcc6c1c7 Add Mode64Bit feature and sink it down to MC layer. 
llvm-svn: 134641
 2011-07-07 21:06:52 +00:00
Evan Cheng 1a72add615 Compute feature bits at time of MCSubtargetInfo initialization. 
llvm-svn: 134606
 2011-07-07 07:07:08 +00:00
Evan Cheng c9c090d7a5 Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency. 
llvm-svn: 134281
 2011-07-01 22:36:09 +00:00
Evan Cheng 0d639a28aa Rename TargetSubtarget to TargetSubtargetInfo for consistency. 
llvm-svn: 134259
 2011-07-01 21:01:15 +00:00
Evan Cheng 54b68e3432 - Added MCSubtargetInfo to capture subtarget features and scheduling 
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

llvm-svn: 134257
 2011-07-01 20:45:01 +00:00
Evan Cheng fe6e405e8c Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to 
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!

llvm-svn: 134127
 2011-06-30 01:53:36 +00:00
Evan Cheng 3a0c5e52ff Remove TargetOptions.h dependency from X86Subtarget. 
llvm-svn: 133726
 2011-06-23 17:54:54 +00:00
Mon P Wang 6f6b44d19d Enable autodetect of popcnt 
llvm-svn: 131476
 2011-05-17 18:33:37 +00:00
Daniel Dunbar cd01ed5bd6 ADT/Triple: Renambe isOSX... methods to isMacOSX for consistency with the OS 
triple component.

llvm-svn: 129838
 2011-04-20 00:14:25 +00:00
Daniel Dunbar 100455a3c8 Target/X86: Eliminate uses of getDarwinVers(). 
llvm-svn: 129813
 2011-04-19 21:04:12 +00:00
Roman Divacky e8a93fe8f0 Stack alignment is 16 bytes on FreeBSD/i386 too. 
llvm-svn: 126226
 2011-02-22 17:30:05 +00:00
Duncan Sands bda7175a43 The stack should be 16 byte aligned on 32 bit solaris. Patch by Yuri. 
llvm-svn: 126130
 2011-02-21 17:37:17 +00:00
Eric Christopher da2d2f4d1f Experiment with changing the default 32-bit linux stack alignment to 
16 bytes for PR8969. Update all testcases accordingly.

llvm-svn: 123367
 2011-01-13 06:47:10 +00:00
Evan Cheng f8b4c0035b Disable auto-detection of AVX support since AVX codegen support is not ready. 
llvm-svn: 121677
 2010-12-13 04:23:53 +00:00
Nate Begeman 8b08f5232b Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. 
llvm-svn: 121439
 2010-12-10 00:26:57 +00:00
Bill Wendling 2bce78e8fc Initialize HasPOPCNT. 
llvm-svn: 120923
 2010-12-04 23:57:24 +00:00
Michael J. Spencer 447762da85 Merge System into Support. 
llvm-svn: 120298
 2010-11-29 18:16:10 +00:00
Anton Korobeynikov db9820ecaa Use rip-rel addressing on win64 by default. For this we just 
defaults to small pic code model.

llvm-svn: 111741
 2010-08-21 17:21:11 +00:00
Bruno Cardoso Lopes 09dc24beac Add x86 CLMUL (Carry-less multiplication) cpu feature 
llvm-svn: 109206
 2010-07-23 01:17:51 +00:00
Eric Christopher d429846eca Have the X86 backend use Triple instead of a string and some enums. 
llvm-svn: 107625
 2010-07-05 19:26:33 +00:00
Chris Lattner faa7bdccbf fix a nasty bug where we were not treating available_externally 
symbols as declarations in the X86 backend.  This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:

symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression

This fixes PR7353.

llvm-svn: 105954
 2010-06-14 20:11:56 +00:00
Dan Gohman dc53f1cb5c FastISel doesn't yet handle callee-pop functions. 
To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.

llvm-svn: 104866
 2010-05-27 18:43:40 +00:00
Evan Cheng 050df1b8de Enable i16 to i32 promotion by default. 
llvm-svn: 102493
 2010-04-28 08:30:49 +00:00
Evan Cheng 9c8cd8c061 isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted. 
llvm-svn: 101979
 2010-04-21 01:47:12 +00:00
Eric Christopher 2ef63183a5 Separate out the AES-NI instructions from the SSE4.2 instructions. Add 
a new subtarget option for AES and check for the support.  Add "westmere"
line of processors and add AES-NI support to the core i7.

Add a couple of TODOs for information I couldn't verify.

llvm-svn: 100231
 2010-04-02 21:54:27 +00:00
Evan Cheng 738b0f9ec7 Nehalem unaligned memory access is fast. 
llvm-svn: 100089
 2010-04-01 05:58:17 +00:00
Evan Cheng bf724b9ee0 Turning off post-ra scheduling for x86. It isn't a consistent win. 
llvm-svn: 98810
 2010-03-18 06:55:42 +00:00