Fix the translation error of the COPY instruction in IR. Previously,
the COPY instruction for float registers would be translated into vmv incorrectly.
This is because the GPRF class inherits from the GPR class, so float registers
were also considered GPR. Now an additional check has been added to translate
COPY instructions accurately.
Summary: LegaLegalized vector parameters, but not been added FileCheck now.
Test Plan: Legalized vector parameters
Differential Revision: http://www.tpt.com/D740
Fix the undefined physical register bug when inserting VMV_V_X instruction
in "checkJoinMBB" funtion to compile with "--verify-machineinstr" parameter.
Summary:
fix addi instruction, there will be a hardware error when immediate is
negative number.
Test Plan: fix add instruction
Reviewers: zhoujing
Subscribers: zhoujing
Differential Revision: http://www.tpt.com/D722
Signed-off-by: qinfan <qinfan.wang@terapines.com>
In standard riscv vararg support, the varstart frame index will be stored in stack,
but because if the design of ventus, some code generation will be like this
vlw.v v0, -44(v8)
vadd.vi v1, v0, 4
vsw.v v1, -44(v8)
\vlw12.v v0, 0(v0)
the last vlw12 instruction is actually illeagl, it should be vlw
In standard riscv vararg support, the varstart frame index will be stored in stack,
but because if the design of ventus, some code generation will be like this
vlw.v v0, -44(v8)
vadd.vi v1, v0, 4
vsw.v v1, -44(v8)
\vlw12.v v0, 0(v0)
the last vlw12 instruction is actually illeagl, it should be vlw
In previous sp initialization, sp points to the same base address for different warps
When different warps ends in different time, the sp pointer in later ended warp will
be changed by former ended warp, we need to initialize sp pointer for different warp
1.Fix errors in VALUrVV class(llvm/lib/Target/RISCV/VentusInstrInfoV.td) where two source operand positions were reversed,
this is differnt from the conventional RISCV instruction.
2.Fix errors in VALUrVF class, same as above.
3.The instructions associated with the above two errors are "vfnmadd.vv", "vfnmadd.vf", etc.
4.Add MC level FileCheck test files to test V instructions.
`void print_ints_uchar(param_t *p, const void *vals , int n, int is_unsigned)`
The second argument is a void pointer, but when we call this function with a non-void
pointer, in traditional C code, this action is legal, but when this pointer carrys different
address space, llvm will report error, we now just avoid this check
`print_ints_uchar(&p, &val, vector_length, is_unsigned)`
In order to prevent new errors from being introduced when modifying the code,
we add regression tests in the project build script and workflow. The
regression tests mainly includes some cases that come with gpu-rodinia and
pocl.
Stack space is shared between different warps, if two warps are executing
different functions, then the access to the return address will conflict,
which will lead the warp executing faster can not find the return address,
so we would like to add a barrier instruction after the lw and before the ret,
to ensure that the warps have the same scope of the sp pointer
zhoujingya
qinfan
Aries