Commit Graph

12 Commits

Author SHA1 Message Date
Kazushi (Jam) Marukawa c84b2c49be [VE] Support inline assembly with vector regsiters
Support inline assembly with vector registers.  Add a regression test also.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D91146
2020-11-10 20:55:38 +09:00
Kazushi (Jam) Marukawa b65ef65b22 [VE] Support inline assembly
Support inline assembly with scalar registers.  Add a regression test also.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D91119
2020-11-10 18:56:22 +09:00
Sergei Trofimovich 1eb812e06d [VE] Fix initializer visibility
Before the change attempt to link libLTO.so against shared
LLVM library failed as:

```
[ 76%] Linking CXX shared library ../../lib/libLTO.so
... /usr/bin/cmake -E cmake_link_script CMakeFiles/LTO.dir/link.txt --verbose=1
c++ -o ...libLTO.so.12git ...ibLLVM-12git.so
ld: CMakeFiles/LTO.dir/lto.cpp.o: in function `llvm::InitializeAllTargetInfos()':
include/llvm/Config/Targets.def:31: undefined reference to `LLVMInitializeVETargetInfo'
```

It happens because on linux llvm build system sets default
symbol visibility to "hidden". The fix is to set visibility
back to "default" for exported APIs with LLVM_EXTERNAL_VISIBILITY.

Bug: https://bugs.llvm.org/show_bug.cgi?id=47847

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D89633
2020-10-19 22:54:41 +01:00
Kazushi (Jam) Marukawa 3c80478d73 [VE] Update branch instructions
Summary:
Changing all mnemonic to match assembly instructions to simplify mnemonic
naming rules. This time update all branch instructions.  This also change
to use %s10 register consistently.

Differential Revision: https://reviews.llvm.org/D78889
2020-04-28 09:41:01 +02:00
Kazushi (Jam) Marukawa d8816261a6 [VE] Create a TargetInfo header. NFC
Summary:
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header in
order to follow other architectures.

Differential Revision: https://reviews.llvm.org/D78543
2020-04-21 11:42:17 +02:00
Kazushi (Jam) Marukawa 015dee1ac8 [VE] Support (m)0 and (m)1 operands
Summary:
VE has special operands to represent 0b000...000111...111 (`(m)0`) and
0b111...111000...000 (`(m)1`) bit sequences.  This patch supports those
operands not only in machine instructions but also in DAG lowering.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D77769
2020-04-09 18:09:00 +02:00
Kazushi (Jam) Marukawa e981a46a77 [VE] Update lea/load/store instructions
Summary:
Modify lea/load/store instructions to accept `disp(index, base)`
style addressing mode (called ASX format).  Also, uniform the
number of DAG nodes to have 3 operands for this ASX format
instructions, and update selectADDR functions to lower
appropriate MI.

Reviewers: arsenm, simoll, k-ishizaka

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D76822
2020-04-06 11:49:46 +02:00
Kazushi (Jam) Marukawa 6bbbead7be [VE] Move VEInstPrinter.cpp and VEInstPrinter.h into MCTargetDesc
Summary:
Move them into MCTargetDesc to follow other architectures (a263aa2).

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D76270
2020-03-17 11:33:54 +01:00
Kazushi (Jam) Marukawa 5526786a56 [VE] TLS codegen
Summary:
Codegen and tests for thread-local storage.
This implements only the general dynamic model due to limitations in nld 2.26.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D74718
2020-02-18 16:09:12 +01:00
Kazushi (Jam) Marukawa 60431bd728 [VE] Support for PIC (global data and calls)
Summary: Support for PIC with tests for global variables and function calls.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D74536
2020-02-14 09:50:02 +01:00
Fangrui Song bcd24b2d43 [AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI* 2020-02-13 22:08:55 -08:00
Kazushi (Jam) Marukawa 064859bde7 [VE] Minimal codegen for empty functions
Summary:
This patch implements minimal VE code generation for empty function bodies (no args, no value return).

Contents

* empty function code generation test.
* Minimal function prologue & epilogue emission
* Instruction formats and instruction definitions as far as required for the empty function prologue & epilogue.
* I64 register class definitions.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D72598
2020-01-15 09:55:16 +01:00