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183 Commits

Author SHA1 Message Date
Jim Grosbach 338de3ee56 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505
 2010-10-27 23:12:14 +00:00
Owen Anderson fadb951e5b Provide correct encodings for NEON vcvt, which has its own special immediate encoding 
for specifying fractional bits for fixed point conversions.

llvm-svn: 117501
 2010-10-27 22:49:00 +00:00
Jim Grosbach f4ea7084c5 JIT imm12 encoding for constant pool entry references. 
llvm-svn: 117483
 2010-10-27 20:39:40 +00:00
Jim Grosbach 333b0a9e74 ARM JIT fix for LDRi12 and company. 
llvm-svn: 117478
 2010-10-27 19:55:59 +00:00
Jim Grosbach ba1c6cd62f The new LDR* instruction patterns should handle the necessary encoding of 
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.

llvm-svn: 117461
 2010-10-27 17:52:51 +00:00
Jim Grosbach 1e4d9a17c2 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Gabor Greif b171ca0a47 fix memory-layout assumption which only holds on little-endian systems 
llvm-svn: 117176
 2010-10-22 23:16:11 +00:00
Jim Grosbach 5edb03ee57 ARM Binary encoding information for BFC/BFI instructions. 
llvm-svn: 117072
 2010-10-21 22:03:21 +00:00
Bill Wendling 058190507b Add encodings for movement between ARM core registers and single-precision 
registers.

llvm-svn: 116961
 2010-10-20 22:44:54 +00:00
Bill Wendling 5f5b922ec6 ARMCodeEmitter::emitMiscInstruction is dead. Long live 
ARMCodeEmitter::emitMiscInstruction!

llvm-svn: 116644
 2010-10-15 23:35:12 +00:00
Jim Grosbach 68a335e185 ARM mode encoding information for UBFX and SBFX instructions. 
llvm-svn: 116588
 2010-10-15 17:15:16 +00:00
Jim Grosbach 062749cb25 Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx' 
pseudonym.

llvm-svn: 116512
 2010-10-14 20:43:44 +00:00
Bill Wendling 0441c6cba0 Add encoding for 'fmstat'. 
llvm-svn: 116466
 2010-10-14 01:19:34 +00:00
Bill Wendling 0825f3e441 - Add encodings for multiply add/subtract instructions in all their glory. 
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.

llvm-svn: 116464
 2010-10-14 01:02:08 +00:00
Jim Grosbach 1e7db68774 Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. 
llvm-svn: 116421
 2010-10-13 19:56:10 +00:00
Jim Grosbach efd5369749 Add the rest of the ARM so_reg encoding options (register shifted register) 
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

llvm-svn: 116377
 2010-10-12 23:53:58 +00:00
Jim Grosbach 12e493ace4 Move the ARM so_imm encoding into a custom operand encoder and remove the 
explicit handling of the instructions referencing it from the MC code
emitter.

llvm-svn: 116367
 2010-10-12 23:18:08 +00:00
Jim Grosbach d9d31dafda Add custom encoder for the 's' bit denoting whether an ARM arithmetic 
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

llvm-svn: 116360
 2010-10-12 23:00:24 +00:00
Jim Grosbach b770c00610 Reapply 116059, this time without the fatfingered pasto at the top. 
''const'ify getMachineOpValue() and associated helpers.'

llvm-svn: 116067
 2010-10-08 17:45:54 +00:00
Jim Grosbach 00351b7731 Reverting 116059. Bots are unhappy with it. 
llvm-svn: 116064
 2010-10-08 17:28:40 +00:00
Jim Grosbach e2d30cd4b5 'const'ify getMachineOpValue() and associated helpers. 
llvm-svn: 116059
 2010-10-08 16:52:44 +00:00
Jim Grosbach a7b6d58f45 Make <target>CodeEmitter::getBinaryCodeForInstr() a const method. 
llvm-svn: 116018
 2010-10-08 00:21:28 +00:00
Jim Grosbach 40e85fbf17 move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper 
functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.

llvm-svn: 114016
 2010-09-15 20:26:25 +00:00
Jim Grosbach 789ca9a1e9 Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. Check 
if the register is a member of the SPR register class directly instead.

llvm-svn: 114012
 2010-09-15 19:44:57 +00:00
Chris Lattner 65b48b5dfc zap dead code. 
llvm-svn: 113073
 2010-09-04 18:12:00 +00:00
Bob Wilson 13ce07fa92 Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like 
all the other LDM/STM instructions.  This fixes asm printer crashes when
compiling with -O0.  I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.

Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier.  Much of the backend
was not aware of these special cases.  The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode.  I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON.  Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.

llvm-svn: 112322
 2010-08-27 23:18:17 +00:00
Bob Wilson 942b10f511 Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid 
printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.

llvm-svn: 111251
 2010-08-17 17:23:19 +00:00
Bob Wilson add513112a Move the ARM SSAT and USAT optional shift amount operand out of the 
instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875
 2010-08-11 23:10:46 +00:00
Bob Wilson 9664984be8 Add a separate ARM instruction format for Saturate instructions. 
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754
 2010-08-11 00:01:18 +00:00
Owen Anderson a7aed18624 Reapply r110396, with fixes to appease the Linux buildbot gods. 
llvm-svn: 110460
 2010-08-06 18:33:48 +00:00
Owen Anderson bda59bd247 Revert r110396 to fix buildbots. 
llvm-svn: 110410
 2010-08-06 00:23:35 +00:00
Owen Anderson 755aceb5d0 Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static 
ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396
 2010-08-05 23:42:04 +00:00
Xerxes Ranby ff66cd43c4 ARMv4 JIT forgets to set the lr register when making a indirect function call. Fixes PR7608 
llvm-svn: 109125
 2010-07-22 17:28:34 +00:00
Bill Wendling 499f797cdd Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and 
thus is a much more meaningful name.

llvm-svn: 108563
 2010-07-16 22:20:36 +00:00
Bob Wilson be157b0ea8 Add support for encoding VDUP (ARM core register) instructions. 
llvm-svn: 107201
 2010-06-29 20:13:29 +00:00
Bob Wilson ab0819e10d Add support for encoding NEON VMOV (from core register to scalar) instructions. 
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.

llvm-svn: 107167
 2010-06-29 17:34:07 +00:00
Bob Wilson 3d12ff797b Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding is 
the same as ARM except that the condition code field is always set to ARMCC::AL.

llvm-svn: 107107
 2010-06-29 00:26:13 +00:00
Bob Wilson 4469a892b4 Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead 
of the Subtarget.

llvm-svn: 107086
 2010-06-28 22:23:17 +00:00
Bob Wilson 544317dfda Refactor encoding function for NEON 1-register with modified immediate format. 
llvm-svn: 107070
 2010-06-28 21:16:30 +00:00
Bob Wilson 584387d5e3 Support Thumb mode encoding of NEON instructions. 
llvm-svn: 107068
 2010-06-28 21:12:19 +00:00
Bob Wilson 0248da9db4 Add support for encoding NEON VMOV (from scalar to core register) instructions. 
llvm-svn: 106938
 2010-06-26 04:07:15 +00:00
Bob Wilson 2530ca0647 Add support for encoding 3-register NEON instructions, and fix 
emitNEON2RegInstruction's handling of 2-address operands.

llvm-svn: 106900
 2010-06-25 22:40:46 +00:00
Bob Wilson e70c8b150b Add support for encoding 2-register NEON instructions. 
llvm-svn: 106891
 2010-06-25 21:17:19 +00:00
Dan Gohman d2d1ae105d Use pre-increment instead of post-increment when the result is not used. 
llvm-svn: 106542
 2010-06-22 15:08:57 +00:00
Bob Wilson 6eae520de9 Add instruction encoding for the Neon VMOV immediate instruction. This changes 
the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction.  This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed.  Testcase for the encoding will follow later when MC has
more support for ARM.

llvm-svn: 105836
 2010-06-11 21:34:50 +00:00
Jim Grosbach 84511e1526 Clean up 80 column violations. No functional change. 
llvm-svn: 105350
 2010-06-02 21:53:11 +00:00
Shih-wei Liao c4376b9b1b Coding style change (Adding 1 missing space.) 
llvm-svn: 104670
 2010-05-26 04:46:50 +00:00
Shih-wei Liao 0568ca0ddc Adding the missing implementation for ARM::SBFX and ARM::UBFX. 
Fixing http://llvm.org/bugs/show_bug.cgi?id=7225.

llvm-svn: 104667
 2010-05-26 03:21:39 +00:00
Shih-wei Liao b6e0bc9457 Adding the missing implementation of Bitfield's "clear" and "insert". 
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222.

llvm-svn: 104653
 2010-05-26 00:25:05 +00:00
Shih-wei Liao e22abfa823 To handle s* registers in emitVFPLoadStoreMultipleInstruction(). 
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221.

llvm-svn: 104652
 2010-05-26 00:02:28 +00:00