348013f829
Add a FIXME.
...
llvm-svn: 116449
2010-10-13 22:55:33 +00:00
0708e74a95
Add operand encoding bits for SMC and SVC in ARM mode.
...
llvm-svn: 116447
2010-10-13 22:38:23 +00:00
16db3287c0
More encoding cleanup. Also add register Rd operands for indirect branches.
...
llvm-svn: 116444
2010-10-13 22:09:34 +00:00
2a4d99ab62
Simplify some ARM encoding information.
...
llvm-svn: 116440
2010-10-13 21:48:54 +00:00
ef83e21b57
Update comment.
...
llvm-svn: 116438
2010-10-13 21:41:51 +00:00
9874b7de58
Add a FIXME. The ADR instruction is a bit odd.
...
llvm-svn: 116437
2010-10-13 21:32:30 +00:00
7e72ec6626
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
...
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
2010-10-13 21:00:04 +00:00
f106ecfa59
Add MC encodings for VCVT* instrunctions.
...
llvm-svn: 116431
2010-10-13 20:58:46 +00:00
fb07ef19cc
Add a FIXME.
...
llvm-svn: 116428
2010-10-13 20:38:04 +00:00
efc066829b
Make a few more bits of some simple instructions explicit. nop, yield, wfe,
...
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.
llvm-svn: 116427
2010-10-13 20:30:55 +00:00
1e7db68774
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
...
llvm-svn: 116421
2010-10-13 19:56:10 +00:00
142e3cbb26
Fix encoding for compares. No Rd register.
...
llvm-svn: 116414
2010-10-13 18:05:25 +00:00
651dc7c9e9
Add ARM mode operand encoding information for ADDE/SUBE instructions.
...
llvm-svn: 116412
2010-10-13 18:00:52 +00:00
dd0821e7ff
Start handling more global variables.
...
llvm-svn: 116401
2010-10-13 09:11:46 +00:00
3912158997
Limit load / store issues (at least until we have a true multi-issue aware scheduler).
...
llvm-svn: 116389
2010-10-13 01:54:21 +00:00
6e27b4f530
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
...
just yet.
llvm-svn: 116386
2010-10-13 01:17:33 +00:00
576fd0b110
Add encodings for VCVT instructions.
...
llvm-svn: 116385
2010-10-13 00:56:35 +00:00
8c519c0d4b
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
...
arithmetic-with-carry-in instructions.
llvm-svn: 116384
2010-10-13 00:50:27 +00:00
da4ddf0fcf
Add VCMPZ and VABS.
...
llvm-svn: 116383
2010-10-13 00:38:07 +00:00
f9ca535495
Refactor VCMP instructions.
...
llvm-svn: 116379
2010-10-13 00:04:29 +00:00
efd5369749
Add the rest of the ARM so_reg encoding options (register shifted register)
...
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
llvm-svn: 116377
2010-10-12 23:53:58 +00:00
7dd8c0b991
Add encodings for VNMUL[SD].
...
llvm-svn: 116375
2010-10-12 23:47:37 +00:00
a06aee826c
Add encodings for VDIV and VMUL.
...
llvm-svn: 116370
2010-10-12 23:22:27 +00:00
12e493ace4
Move the ARM so_imm encoding into a custom operand encoder and remove the
...
explicit handling of the instructions referencing it from the MC code
emitter.
llvm-svn: 116367
2010-10-12 23:18:08 +00:00
42200bcaea
Refactor some of the encoding logic into a base class. This keeps us from having
...
to add 10+ lines to every instruction.
It may turn out that we can move this base class into it's parent class.
llvm-svn: 116362
2010-10-12 23:06:54 +00:00
d9d31dafda
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
...
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
llvm-svn: 116360
2010-10-12 23:00:24 +00:00
646a506724
Add encoding for VSUB and VCMP.
...
Fear not! I'm going to try a refactoring right now. :)
llvm-svn: 116359
2010-10-12 22:55:35 +00:00
ac6cd00706
Encoding for VADDD. Plus a test for the VFP instructions.
...
llvm-svn: 116348
2010-10-12 22:08:41 +00:00
98c29d732d
Split out the "size" field from the encoding. The newer documentation has it as
...
a separate bit in the coding.
llvm-svn: 116347
2010-10-12 22:03:19 +00:00
22e051eef0
Fix thinko in arm fast isel alloca rewrite.
...
llvm-svn: 116339
2010-10-12 21:23:43 +00:00
576640f0e3
Encoding for ARM-mode VADD.F32 instruction.
...
llvm-svn: 116338
2010-10-12 21:22:40 +00:00
0e57a9f7a9
Add MOVi ARM encoding.
...
llvm-svn: 116321
2010-10-12 18:09:12 +00:00
feeae27ad9
Nuke unused wrapper function.
...
llvm-svn: 116318
2010-10-12 17:53:25 +00:00
6fead930af
Add encoding information for the remainder of the generic arithmetic
...
ARM instructions.
llvm-svn: 116313
2010-10-12 17:11:26 +00:00
dd6eb5b5a1
PR8359: The ARM backend may end up allocating registers D16 to D31 when
...
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!
llvm-svn: 116310
2010-10-12 16:22:47 +00:00
7cd5cda6bb
Rework alloca handling so that we can load or store from casted
...
address that we've looked through.
Fixes compilation problems in tramp3d from earlier patch.
llvm-svn: 116296
2010-10-12 05:39:06 +00:00
db3bcc9910
Handle a wider arrangement of loads.
...
llvm-svn: 116284
2010-10-12 00:43:21 +00:00
e790afcbe1
More ARM scheduling itinerary fixes.
...
llvm-svn: 116266
2010-10-11 23:41:41 +00:00
b7c2962d20
MC machine encoding for simple aritmetic instructions that use a shifted
...
register operand.
llvm-svn: 116259
2010-10-11 23:16:21 +00:00
109ff296c8
Second set of ARM/MC/ELF changes.
...
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)
llvm-svn: 116257
2010-10-11 23:01:44 +00:00
94ad008beb
Proper VST scheduling itineraries.
...
llvm-svn: 116251
2010-10-11 22:03:18 +00:00
d42340ecfd
Use a sane mechanism for that assert.
...
llvm-svn: 116249
2010-10-11 22:01:22 +00:00
72b91c1765
We're not going to handle dynamic allocas anywhere else.
...
llvm-svn: 116240
2010-10-11 21:37:35 +00:00
71ef1af66b
Make sure that the call stack adjustments have default operands. Also
...
leave custom lowerings for later.
Fixes some nightly tests.
llvm-svn: 116232
2010-10-11 21:20:02 +00:00
e2a0b6841a
Found a bug turning this on by default. Disable again for now.
...
llvm-svn: 116220
2010-10-11 20:26:21 +00:00
46cc854e5e
Fix help text.
...
llvm-svn: 116218
2010-10-11 20:15:02 +00:00
5501b7e805
Change flag from Enable to Disable since we're enabled by default.
...
Also don't use fast-isel on non-darwin since it's untested.
llvm-svn: 116217
2010-10-11 20:05:22 +00:00
5476a274c8
More binary encoding stuff, taking advantage of the new "by name" operand
...
matching in tblgen to do the predicate operand.
llvm-svn: 116213
2010-10-11 18:51:51 +00:00
2276e87a65
Turn on arm fast isel by default.
...
llvm-svn: 116212
2010-10-11 18:48:18 +00:00
0f5bfd27a3
MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.
...
llvm-svn: 116201
2010-10-11 11:36:19 +00:00
e1bcb43bb9
Copy and pasteo.
...
llvm-svn: 116198
2010-10-11 08:40:05 +00:00
7ac602bc8e
Whitespace cleanup in ARM fast isel.
...
llvm-svn: 116197
2010-10-11 08:38:55 +00:00
eae1b38550
Add srem libcall support to ARM fast isel.
...
llvm-svn: 116196
2010-10-11 08:37:26 +00:00
e11017c19e
Add i8 sdiv support for ARM fast isel.
...
llvm-svn: 116195
2010-10-11 08:31:54 +00:00
511aa31965
Implement select handling for ARM fast-isel.
...
llvm-svn: 116194
2010-10-11 08:27:59 +00:00
d7a404d85f
Add VLD4 scheduling itineraries.
...
llvm-svn: 116143
2010-10-09 04:07:58 +00:00
a762400bed
Finish vld3 and vld4.
...
llvm-svn: 116140
2010-10-09 01:45:34 +00:00
4187f4942e
Complete vld2 instruction itineries.
...
llvm-svn: 116136
2010-10-09 01:26:12 +00:00
1c7fa43e6f
Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1.
...
llvm-svn: 116135
2010-10-09 01:15:04 +00:00
05f13e94bf
Correct some load / store instruction itinerary mistakes:
...
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
llvm-svn: 116134
2010-10-09 01:03:04 +00:00
59ebe44049
Check to make sure that the iterator isn't at the beginning of the basic block
...
before decrementing. <rdar://problem/8529919>
llvm-svn: 116126
2010-10-09 00:03:48 +00:00
548587c31c
Fix the store part of this as well. Fixes smg2000.
...
llvm-svn: 116123
2010-10-08 23:52:16 +00:00
c43c930690
Implement a few more binary encoding bits. Still very early stage proof-of-
...
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
llvm-svn: 116112
2010-10-08 21:45:55 +00:00
b770c00610
Reapply 116059, this time without the fatfingered pasto at the top.
...
''const'ify getMachineOpValue() and associated helpers.'
llvm-svn: 116067
2010-10-08 17:45:54 +00:00
00351b7731
Reverting 116059. Bots are unhappy with it.
...
llvm-svn: 116064
2010-10-08 17:28:40 +00:00
e2d30cd4b5
'const'ify getMachineOpValue() and associated helpers.
...
llvm-svn: 116059
2010-10-08 16:52:44 +00:00
056b694de1
Change register allocation order for ARM VFP and NEON registers to put the
...
callee-saved registers at the end of the lists. Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases. Thanks to
Jakob for helping me realize the problem.
Most of this patch is fixing the testsuite. There are quite a few places
where we're checking for specific registers. I changed those to wildcards
in places where that doesn't weaken the tests. The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.
llvm-svn: 116055
2010-10-08 06:15:13 +00:00
15bc2438d9
Move to thumb2 loads, fixes a problem with incoming registers
...
as thumb1.
Fixes lencod.
llvm-svn: 116027
2010-10-08 01:13:17 +00:00
0bb2f9afa9
Enable binary encoding of some simple instructions.
...
llvm-svn: 116022
2010-10-08 00:39:21 +00:00
a7b6d58f45
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
...
llvm-svn: 116018
2010-10-08 00:21:28 +00:00
412e37bd34
Code refactoring.
...
llvm-svn: 116002
2010-10-07 23:12:15 +00:00
91029094e0
Trivial MC code emitter shell. No instruction forms actually handled yet.
...
llvm-svn: 115993
2010-10-07 22:12:50 +00:00
8aed386d82
Include the auto-generated bits for machine encoding.
...
llvm-svn: 115987
2010-10-07 21:57:55 +00:00
3e1e447ca2
Remember to promote load/store types for stack to register size.
...
llvm-svn: 115984
2010-10-07 21:40:18 +00:00
07b5b1802e
ARM instruction don't have instruction prefixes, so remove the helper functions
...
for them from the MCCodeEmitter.
llvm-svn: 115975
2010-10-07 20:41:30 +00:00
a2583ea9f2
Use the correct register class for load instructions - fixes
...
compilation of MultiSource/Benchmarks/Bullet.
llvm-svn: 115907
2010-10-07 05:50:44 +00:00
76a9752d45
Use the correct register class here.
...
llvm-svn: 115906
2010-10-07 05:39:19 +00:00
a98be90efe
Use the thumb2 conditional move instruction.
...
llvm-svn: 115905
2010-10-07 05:31:49 +00:00
6d74673366
Remove in-progress assertion, add TODO.
...
llvm-svn: 115904
2010-10-07 05:14:08 +00:00
1958cefd69
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
...
llvm-svn: 115898
2010-10-07 01:50:48 +00:00
5b255c2dd6
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
...
llvm-svn: 115890
2010-10-07 00:53:56 +00:00
742adc328a
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
...
llvm-svn: 115884
2010-10-07 00:42:42 +00:00
25cd3bfbd7
remove trailing whitespace
...
llvm-svn: 115860
2010-10-06 22:46:47 +00:00
bff84d418f
First in a sequence of ARM/MC/*ELF* specific work.
...
Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored
llvm-svn: 115859
2010-10-06 22:36:46 +00:00
24ab1ce8c2
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
...
llvm-svn: 115853
2010-10-06 22:01:26 +00:00
f49540cb4f
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
...
llvm-svn: 115845
2010-10-06 21:36:43 +00:00
2c95027258
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
...
"lane" operand modifier.
llvm-svn: 115843
2010-10-06 21:22:32 +00:00
2e3e2a006b
Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
...
pseudo instructions.
llvm-svn: 115840
2010-10-06 21:16:16 +00:00
233b3a2f95
Add a 'pattern' arg to the ARM PseudoNeonI class.
...
llvm-svn: 115831
2010-10-06 20:36:55 +00:00
8025f89860
target operand flag values aren't a bitmask
...
llvm-svn: 115798
2010-10-06 16:51:55 +00:00
49d4c0bd18
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
04c342ea20
replace stuff like:
...
let AsmString = !strconcat(
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
!strconcat("\t", asm));
with:
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
:)
llvm-svn: 115720
2010-10-06 00:05:18 +00:00
b9f2d50d5f
Comment out fastisel debugging message.
...
llvm-svn: 115717
2010-10-05 23:50:58 +00:00
8cfc459274
Random cleanup and make the intermediate register in fptosi a
...
32-bit fp reg, not 64-bit.
Fixes SingleSource.
llvm-svn: 115711
2010-10-05 23:13:24 +00:00
e929899a3f
Increase the number of bits used internally by the ARM target to represent the
...
addressing mode from four to five.
llvm-svn: 115645
2010-10-05 18:14:55 +00:00
70ac5fa42c
fix MSVC 2010 build.
...
llvm-svn: 115594
2010-10-05 06:00:43 +00:00
e7f00cbb7c
Cleanup Whitespace.
...
llvm-svn: 115593
2010-10-05 06:00:33 +00:00
66e08d43d2
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
...
so and also change X86 for consistency.
Investigating if this can be improved a bit.
llvm-svn: 115469
2010-10-03 18:59:45 +00:00
73eac2aadf
Major changes to Cortex-A9 itinerary.
...
1. Model dual issues as two FUs.
2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a
dependent pipeline on ALU0.
The changes do not have much impact on codegen right now. But I plan to make
pre-RA scheduler multi-issue aware which should take good advantage of the
changes.
llvm-svn: 115457
2010-10-03 02:03:59 +00:00
7787f79f21
Start on lowering global addresses.
...
llvm-svn: 115390
2010-10-02 00:32:44 +00:00
ff1751c0a6
PrintSpecial() can go away now.
...
llvm-svn: 115376
2010-10-01 23:27:48 +00:00
83a5ec8fe0
Stub out constant GV handling, fixes C++ eh tests.
...
llvm-svn: 115375
2010-10-01 23:24:42 +00:00
fae8305e2b
Nuke the rest of the :comment references
...
llvm-svn: 115373
2010-10-01 23:21:38 +00:00
c13194254b
Nuke a bunch of no-longer-needed comment-only asm strings.
...
llvm-svn: 115370
2010-10-01 23:09:33 +00:00
a317815463
Fix r115332: correctly model AGU / NEON mux.
...
llvm-svn: 115365
2010-10-01 22:52:29 +00:00
f31f33ea89
Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now,
...
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.
llvm-svn: 115364
2010-10-01 22:45:50 +00:00
0e854f3d43
Rename the AsmPrinter directory to InstPrinter for those targets that have
...
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
llvm-svn: 115360
2010-10-01 22:39:28 +00:00
1969887fc6
Fix scheduling infor for vmovn and vshrn which I broke accidentially.
...
llvm-svn: 115354
2010-10-01 21:48:06 +00:00
f3179567de
Add operand cycles for vldr / vstr.
...
llvm-svn: 115353
2010-10-01 21:40:30 +00:00
9d0136274b
Direct calls only for arm fast isel for now.
...
llvm-svn: 115350
2010-10-01 21:33:12 +00:00
2a5d764858
NEON scheduling info fix. vmov reg, reg are single cycle instructions.
...
llvm-svn: 115344
2010-10-01 20:50:58 +00:00
6080da7a79
Fix thinko on store instructions. Fixes test_indvars failure.
...
llvm-svn: 115342
2010-10-01 20:46:04 +00:00
2ecba4a07e
Make the spelling of the flags for old-style if-conversion heuristics consistent between ARM and Thumb2.
...
llvm-svn: 115341
2010-10-01 20:33:47 +00:00
671d57865e
Provide an option to restore old-style if-conversion heuristics for Thumb2.
...
llvm-svn: 115339
2010-10-01 20:28:06 +00:00
89e6f6759f
Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly.
...
llvm-svn: 115332
2010-10-01 19:41:46 +00:00
05ed521a88
grammar
...
llvm-svn: 115314
2010-10-01 14:57:48 +00:00
c1e209d40e
Implement double return values in calls. Fixes
...
SingleSource/Regression/C/casts.c.
llvm-svn: 115246
2010-10-01 00:00:11 +00:00
b9b63ee031
Temporarily add a flag to make it easier to compare the new-style ARM if
...
conversion heuristics to the old-style ones.
llvm-svn: 115239
2010-09-30 23:48:38 +00:00
56094ff402
Movement and cleanup.
...
llvm-svn: 115225
2010-09-30 22:34:19 +00:00
78f8d4eaf0
Start of generalized call support for ARM fast isel.
...
llvm-svn: 115203
2010-09-30 20:49:44 +00:00
c8e2e9d830
Nuke a few more unused asm strings
...
llvm-svn: 115193
2010-09-30 19:53:58 +00:00
7e872969ce
Move getPointerSize() to the base class since it's not dependent on MachO
...
vs. ELF
llvm-svn: 115180
2010-09-30 17:45:51 +00:00
5a5ddc402e
Remove extraneous ';'
...
llvm-svn: 115176
2010-09-30 17:19:17 +00:00
b9429179f9
The asm strings are never used at all, so just nuke 'em entirely.
...
llvm-svn: 115160
2010-09-30 16:56:53 +00:00
bad267fa05
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
...
for the dwarf .loc support to emit dwarf line number tables.
llvm-svn: 115153
2010-09-30 16:38:07 +00:00
136ed51b08
80 column fix
...
llvm-svn: 115149
2010-09-30 15:25:22 +00:00
6c233c141e
Fix two tiny issues (ARM does not need COFF) and comment sanity.
...
llvm-svn: 115147
2010-09-30 14:58:19 +00:00
689651c767
trailing whitespace
...
llvm-svn: 115136
2010-09-30 03:21:00 +00:00
58bce99385
Remove misplaced ';'. Make buildbots happy, hopefully.
...
llvm-svn: 115135
2010-09-30 03:20:34 +00:00
645f6c2bef
Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()
...
Small test for sanity check of resulting ARM .s file.
Tested against -r115129.
llvm-svn: 115133
2010-09-30 02:45:56 +00:00
4a9cb8f10e
Go ahead and jump!
...
Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
llvm-svn: 115130
2010-09-30 02:18:06 +00:00
b32124545b
I added a new file ARMAsmBackend which stubs out in similar ways to
...
the eqv X86 class.
For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend
(also mimicking X86)
Tested against -r115126
llvm-svn: 115129
2010-09-30 02:17:26 +00:00
2ff7de0264
Now that the pseudos that needed this are all custom lowered, we can go back
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to an empty PrintSpecial()
llvm-svn: 115128
2010-09-30 02:02:22 +00:00
080fdf4609
Nuke it from orbit. It's the only way to be sure.
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(Kill the dead non-MC asm printer for the ARM target.)
llvm-svn: 115127
2010-09-30 01:57:53 +00:00
2fb20b1d37
ARM instruction itinerary fixes:
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1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
llvm-svn: 115121
2010-09-30 01:08:25 +00:00
7939806ecc
Refactor arm fast isel libcall handling so that pieces can be used
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for generic call handling.
llvm-svn: 115105
2010-09-29 23:11:09 +00:00
4a010fd1ea
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
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pipeline forwarding path.
llvm-svn: 115098
2010-09-29 22:42:35 +00:00
b024be3162
Add a convenience variable so I'm not chasing all over looking for
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a context.
llvm-svn: 115094
2010-09-29 22:24:45 +00:00
0860520527
Add specializations of addrmode2 that allow differentiating those forms
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which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.
llvm-svn: 115066
2010-09-29 19:03:54 +00:00
97bf273870
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
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LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
llvm-svn: 115047
2010-09-29 17:54:10 +00:00
c7b10f3745
Add braces for legibility.
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llvm-svn: 115043
2010-09-29 17:32:29 +00:00
05eccf0e44
One Printer to rule them all, One Printer to find them,
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One Printer to lower them all and in the back end bind them.
(Remove option to use the old non-MC asm printer.)
llvm-svn: 115038
2010-09-29 15:23:40 +00:00
d36e3e8850
improve heuristics to find the 'and' corresponding to 'tst' to also catch opportunities on thumb2
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added some doxygen on the way
llvm-svn: 115033
2010-09-29 10:12:08 +00:00
a63292a3ca
implement rdar://8456378 and PR7557 - support for the fstsw,
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an instruction that requires a WHOLE NEW wonderful kind of alias.
llvm-svn: 115015
2010-09-29 01:50:45 +00:00
b44fd24fc1
change the protocol TargetAsmPArser::MatchInstruction method to take an
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MCStreamer to emit into instead of an MCInst to fill in. This allows the
matcher extra flexibility and is more convenient.
llvm-svn: 115014
2010-09-29 01:42:58 +00:00
3a7e8cd6bd
Rework comparison handling to set a register on true/false. This avoids
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problems with phi-nodes in blocks that have hard and not virtual registers.
Accordingly update branch handling to compensate.
llvm-svn: 115013
2010-09-29 01:14:47 +00:00
edd4b600f3
Remove unnecessary set ahead of time.
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llvm-svn: 115011
2010-09-29 00:50:57 +00:00
2259d67a33
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
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llvm-svn: 115010
2010-09-29 00:49:25 +00:00
2c8e7f421c
Remove assert, add comment.
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llvm-svn: 115009
2010-09-29 00:49:09 +00:00
c35d7bbe43
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
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llvm-svn: 115008
2010-09-29 00:27:46 +00:00
0097dd0d5a
Add support to model pipeline bypass / forwarding.
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llvm-svn: 115005
2010-09-28 23:50:49 +00:00
a86a6d2fed
32-bit constant ints only for now.
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llvm-svn: 115001
2010-09-28 22:47:54 +00:00
b4b12535e8
Removed a bunch of unnecessary target_link_libraries.
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llvm-svn: 114999
2010-09-28 22:39:14 +00:00
a3181e2d79
Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
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cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability.
Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.
llvm-svn: 114995
2010-09-28 21:57:50 +00:00
953b1afd5f
Integer materialization needed the same thinko change.
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llvm-svn: 114994
2010-09-28 21:55:34 +00:00
7d483d352b
Resolve this GCC warning:
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ARMTargetMachine.cpp:53: error: control reaches end of non-void function
llvm-svn: 114992
2010-09-28 21:40:26 +00:00
81bdc93bbb
User proper libcall names & condcodes while compiling for ARM EABI.
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Patch by Evzen Muller!
llvm-svn: 114991
2010-09-28 21:39:26 +00:00
88af7d00fc
Part one of switching to using a more sane heuristic for determining if-conversion profitability.
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Rather than having arbitrary cutoffs, actually try to cost model the conversion.
For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.
llvm-svn: 114973
2010-09-28 18:32:13 +00:00
45c83d496f
Factor out dbg_value comment printing and teach MC asm printing to use it.
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This should make the arm-linux self-host buildbot happy again.
llvm-svn: 114964
2010-09-28 17:05:56 +00:00
3da4255d07
Add ARM Disassembler to the CMake build.
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llvm-svn: 114949
2010-09-28 11:48:19 +00:00
bf86fd3c47
80-col fixups.
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llvm-svn: 114943
2010-09-28 04:18:29 +00:00
3dc97324c1
Add a command line option "-arm-strict-align" to disallow unaligned memory
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accesses for ARM targets that would otherwise allow it. Radar 8465431.
llvm-svn: 114941
2010-09-28 04:09:35 +00:00
7990df1ae2
Rework builtin handling and call setup. The builtin handling
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now takes a libcall operand, sets up the arguments correctly and
handles stack adjustments.
llvm-svn: 114934
2010-09-28 01:21:42 +00:00
e68635acdb
Fix typo.
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llvm-svn: 114931
2010-09-28 00:35:33 +00:00
6f98bfd870
Fix fp constant loads to have a destination register.
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llvm-svn: 114930
2010-09-28 00:35:09 +00:00
175d6411c8
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
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enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
llvm-svn: 114915
2010-09-27 22:28:11 +00:00
9e9ed98305
ARM-mode eh.sjlj.longjmp MC lowering
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llvm-svn: 114896
2010-09-27 21:47:04 +00:00
11fed543c9
Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
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enable it for real. Leaving the CL option in place to it's easy to disable it
again if (when) testers find something I've missed.
llvm-svn: 114892
2010-09-27 21:28:44 +00:00
6b2aaf1a36
Hard to imagine there are still people using inferior compilers.
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llvm-svn: 114862
2010-09-27 20:12:58 +00:00
69aa15155f
Odd additional stub framework for the ARM MC ELF emission.
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llc now recognizes the "intent" to support MC/obj emission for ARM, but
given that they are all stubs, it asserts on --filetype=obj --march=arm
Patch by Jason Kim.
llvm-svn: 114856
2010-09-27 18:31:37 +00:00
0720611e3a
Insert missing coherency in comment. Add a quick check for hardware
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divide support also.
llvm-svn: 114813
2010-09-27 06:08:12 +00:00
29ab6d1f82
Mass rename for Jim.
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llvm-svn: 114812
2010-09-27 06:02:23 +00:00
48cc21620f
Fix IIC_iEXTAr itinerary class of Cortex-A9.
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llvm-svn: 114784
2010-09-25 01:09:28 +00:00
8f9a2244fc
Remove a unused instruction itinerary class.
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llvm-svn: 114782
2010-09-25 01:06:02 +00:00
62d626ce86
Fix zero and sign extension instructions scheduling itineraries.
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llvm-svn: 114780
2010-09-25 00:49:35 +00:00
e37da03e60
More pseudo instruction scheduling itinerary fixes.
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llvm-svn: 114768
2010-09-24 22:41:41 +00:00
1d35ad62cc
Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions.
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llvm-svn: 114766
2010-09-24 22:03:46 +00:00
4a6ab13fb9
Add ARM explicit MCInst lowering for the Thumb eh.sjlj.setjmp sequence.
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llvm-svn: 114758
2010-09-24 20:47:58 +00:00
dbcc4b4d4d
Enable code placement optimization pass for ARM.
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llvm-svn: 114746
2010-09-24 19:07:23 +00:00
40a4222996
Fix a potential null dereference bug.
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llvm-svn: 114723
2010-09-24 05:18:35 +00:00
2c5df619c4
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
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reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
llvm-svn: 114710
2010-09-23 23:45:25 +00:00
7fbbe9a43a
Set alignment operand for NEON VST instructions.
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llvm-svn: 114709
2010-09-23 23:42:37 +00:00
c0aed7179a
ARM-mode eh.sjlj.setjmp pseudo MC-inst lowering expansion
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llvm-svn: 114707
2010-09-23 23:33:56 +00:00
2f3728f576
#+4 --> #4 for consistency with other asm output
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llvm-svn: 114706
2010-09-23 23:32:38 +00:00
07f07290d8
Fix formatting of output .s code
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llvm-svn: 114705
2010-09-23 23:03:26 +00:00
bd57e0ce3d
Add isConditionalMove bits to X86 and ARM instructions.
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llvm-svn: 114703
2010-09-23 22:57:01 +00:00
9eeb890172
Set alignment operand for NEON VLD instructions.
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llvm-svn: 114696
2010-09-23 21:43:54 +00:00
7d34837676
never mind. I can't read, apparently
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llvm-svn: 114689
2010-09-23 19:42:17 +00:00
1596f7f6f3
Fix r114632. Return if the only terminator is an unconditional branch after the redundant ones are deleted.
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llvm-svn: 114688
2010-09-23 19:42:03 +00:00
836341a17a
Fix opcode value for the 'trap' instruction, keeping the type suffix on the
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constant. Hopefully the non-Darwin bots will like it...
llvm-svn: 114687
2010-09-23 19:32:40 +00:00
3d50a3e237
explicit 'unsigned long' on constant value. Hopefully make bots happier.
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llvm-svn: 114686
2010-09-23 19:08:04 +00:00
e38495dbc0
Unbreak build. Jim, please review.
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llvm-svn: 114684
2010-09-23 18:57:26 +00:00
8503054410
Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't
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(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.
Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.
llvm-svn: 114679
2010-09-23 18:05:37 +00:00
ea20e257b2
nuke unused var
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llvm-svn: 114676
2010-09-23 17:58:00 +00:00
66c8cd2b32
If there are multiple unconditional branches terminating a block, eliminate all
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but the first one. Those will never be executed. There was logic to do this
but it was faulty.
llvm-svn: 114632
2010-09-23 06:54:40 +00:00
85dcd3d0f4
Add support for ELF PLT references for ARM MC asm printing. Adding a
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new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure
there's a more straightforward way to get the printing difference captured.
(i.e., x86 uses @PLT, ARM uses (PLT)).
llvm-svn: 114613
2010-09-22 23:27:36 +00:00
a9424d4f2f
Enable a few additional asserts in MC instruction lowering.
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llvm-svn: 114601
2010-09-22 23:01:28 +00:00
463a05342a
Change VDUPLANE DAG combiner to just return the result instead of calling
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CombineTo to avoid putting the result on the worklist. I don't think it makes
much difference for now, but it might help someday as we add more DAG
combine optimizations.
llvm-svn: 114595
2010-09-22 22:27:30 +00:00
2280674fa9
Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing one
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of those. Refactor to share code for handling BUILD_VECTOR(VMOVRRD).
I don't have a testcase that exercises this, but it seems like an obvious
good thing to do.
llvm-svn: 114589
2010-09-22 22:09:21 +00:00
1f57cc4a59
add FIXME
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llvm-svn: 114578
2010-09-22 20:55:15 +00:00
Jim Grosbach