914223010c
Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
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for the assembler and disassembler. Which were not being set/read correctly
for offsets greater than 22 bits in some cases.
Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!
llvm-svn: 156118
2012-05-03 22:41:56 +00:00
9560af848c
Fixed disassembler for vstm/vldm ARM VFP instructions.
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llvm-svn: 156077
2012-05-03 16:38:40 +00:00
9d8f6f3d9d
ARM: Tweak tADDrSP definition for consistent operand order.
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Make the operand order of the instruction match that of the asm syntax.
llvm-svn: 155747
2012-04-27 23:51:33 +00:00
f435b09eaf
Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst.
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llvm-svn: 155700
2012-04-27 08:42:59 +00:00
e9600009e9
Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector
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llvm-svn: 155439
2012-04-24 11:13:20 +00:00
ca45af9a75
Added support for disassembling unpredictable swp/swpb ARM instructions.
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llvm-svn: 155004
2012-04-18 14:18:57 +00:00
41f1fcd80e
Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
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llvm-svn: 155001
2012-04-18 13:12:50 +00:00
29ae538647
Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
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instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .
llvm-svn: 154884
2012-04-17 00:49:27 +00:00
40d4e47003
Fix a few more places in the ARM disassembler so that branches get
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symbolic operands added when using the C disassembler API.
llvm-svn: 154628
2012-04-12 23:13:34 +00:00
72f18bbcff
Fixed a case of ARM disassembly getting an assert on a bad encoding
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of a VST instruction.
llvm-svn: 154544
2012-04-11 22:40:17 +00:00
d2980cd041
Fix ARM disassembly of VLD instructions with writebacks. And add test a case
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for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .
llvm-svn: 154459
2012-04-11 00:25:40 +00:00
7a3973d3e0
ARMDisassembler: drop bogus dependency on ARMCodeGen
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And indirectly, a dependency on most of the core LLVM optimization
libraries.
llvm-svn: 153957
2012-04-03 15:48:14 +00:00
f6e7e12f75
Remove unnecessary llvm:: qualifications
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llvm-svn: 153500
2012-03-27 07:21:54 +00:00
4afd7d2316
Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
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llvm-svn: 153252
2012-03-22 14:14:49 +00:00
d213f2111a
Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM
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llvm-svn: 153251
2012-03-22 13:24:43 +00:00
7e7d5eefb2
Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test
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case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .
llvm-svn: 153218
2012-03-21 20:54:32 +00:00
32a49333ec
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
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llvm-svn: 153089
2012-03-20 15:54:56 +00:00
ca658c2264
Use uint16_t to store registers and opcode in static tables in the target specific backends.
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llvm-svn: 152537
2012-03-11 07:16:55 +00:00
eed9992b26
Tidy up. Remove dead code that slipped into previous commit.
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llvm-svn: 152184
2012-03-07 00:52:39 +00:00
ed428bc1ce
ARM more NEON VLD/VST composite physical register refactoring.
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Register pair, all lanes subscripting.
llvm-svn: 152157
2012-03-06 23:10:38 +00:00
13a292cc74
ARM refactor more NEON VLD/VST instructions to use composite physregs
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Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
llvm-svn: 152150
2012-03-06 22:01:44 +00:00
520eb3ba8a
Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.
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llvm-svn: 152127
2012-03-06 18:33:12 +00:00
e5307f9019
ARM Refactor VLD/VST spaced pair instructions.
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Use the new composite physical registers.
llvm-svn: 152063
2012-03-05 21:43:40 +00:00
c988e0c521
ARM refactor away a bunch of VLD/VST pseudo instructions.
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With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
llvm-svn: 152045
2012-03-05 19:33:30 +00:00
56b662ce0f
Make MemoryObject accessor members const again
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llvm-svn: 151687
2012-02-29 01:09:06 +00:00
1489b523c3
Fix the symbolic operand added for the C disassmbler API for the ARM bl
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thumb instruction. The PC adjustment is +4 in Thumb mode and +8 in ARM mode.
llvm-svn: 151530
2012-02-27 18:15:15 +00:00
6fbcd8d439
Updated the llvm-mc disassembler C API to support for the X86 target.
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rdar://10873652
As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back. If there is a
getOpInfo call back that is tried first and then if that gets no information
then the SymbolLookUp is called. I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo. And also don't use any
values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683
For the X86 target also fixed bugs so the annotations get printed.
Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions. rdar://10878166
llvm-svn: 151267
2012-02-23 18:18:17 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
428704eb52
Make the EDis tables const.
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llvm-svn: 150304
2012-02-11 14:51:07 +00:00
e55c556a24
Convert assert(0) to llvm_unreachable
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llvm-svn: 149961
2012-02-07 02:50:20 +00:00
8b2dcad4b5
Enable streaming of bitcode
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This CL delays reading of function bodies from initial parse until
materialization, allowing overlap of compilation with bitcode download.
llvm-svn: 149918
2012-02-06 22:30:29 +00:00
46a9f016c5
More dead code removal (using -Wunreachable-code)
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llvm-svn: 148578
2012-01-20 21:51:11 +00:00
4a5c887370
ARM NEON VTBL/VTBX assembly parsing and encoding.
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llvm-svn: 146691
2011-12-15 22:27:11 +00:00
88ac761aa4
ARM NEON refactor VST2 w/ writeback instructions.
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In addition to improving the representation, this adds support for assembly
parsing of these instructions.
llvm-svn: 146588
2011-12-14 21:32:11 +00:00
8d24618975
ARM NEON VST2 assembly parsing and encoding.
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Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
d146a02c79
ARM assembly parsing and encoding for VLD2 with writeback.
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Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
llvm-svn: 146278
2011-12-09 21:28:25 +00:00
23c30b90e3
Remove unused variable
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llvm-svn: 145517
2011-11-30 19:53:11 +00:00
a68c9a847e
ARM parsing for VLD1 all lanes, with writeback.
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llvm-svn: 145510
2011-11-30 19:35:44 +00:00
5ee209ce3a
ARM assembly parsing and encoding for four-register VST1.
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llvm-svn: 145450
2011-11-29 22:58:48 +00:00
98d032fd67
ARM assembly parsing and encoding for three-register VST1.
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llvm-svn: 145442
2011-11-29 22:38:04 +00:00
05060f0748
Fix a misplaced paren bug.
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llvm-svn: 144692
2011-11-15 20:30:41 +00:00
0ac9058f89
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
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llvm-svn: 144683
2011-11-15 19:55:00 +00:00
8ca13deecf
Re-apply 144430, this time with the associated isel and disassmbler bits.
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Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'
llvm-svn: 144437
2011-11-12 00:31:53 +00:00
48b5bbffed
Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
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llvm-svn: 144384
2011-11-11 12:39:41 +00:00
ec5c5f7008
The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552.
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llvm-svn: 143553
2011-11-02 17:46:18 +00:00
fad59dab62
Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case.
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llvm-svn: 143552
2011-11-02 17:41:23 +00:00
69e54a740c
Fix disassembly of some VST1 instructions.
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llvm-svn: 143507
2011-11-01 22:18:13 +00:00
05df460269
ARM VST1 w/ writeback assembly parsing and encoding.
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llvm-svn: 143369
2011-10-31 21:50:31 +00:00
40703f4252
More not-crashing NEON disassembly updates for the vld refactoring.
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llvm-svn: 143351
2011-10-31 17:17:32 +00:00
dde461c8b1
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
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llvm-svn: 143208
2011-10-28 18:02:13 +00:00
8a6ebd085a
Add some NEON stores to the VLD decoding hook that were accidentally omitted previously.
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llvm-svn: 143162
2011-10-27 22:53:10 +00:00
17ec1a19e5
ARM assembly parsing and encoding for VLD1 with writeback.
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Four entry register lists.
llvm-svn: 142882
2011-10-25 00:14:01 +00:00
92fd05ecdc
ARM assembly parsing and encoding for VLD1 w/ writeback.
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Three entry register list variation.
llvm-svn: 142876
2011-10-24 23:26:05 +00:00
2098cb1e6f
ARM refactor am6offset usage for VLD1.
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Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
llvm-svn: 142853
2011-10-24 21:45:13 +00:00
295b1e84ce
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
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llvm-svn: 142817
2011-10-24 18:04:29 +00:00
0d6d098841
Move various generated tables into read-only memory, fixing up const correctness along the way.
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llvm-svn: 142726
2011-10-22 16:50:00 +00:00
11c0b347c6
Assembly parsing for 4-register sequential variant of VLD2.
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llvm-svn: 142704
2011-10-21 23:58:57 +00:00
118b38cbf1
Assembly parsing for 2-register sequential variant of VLD2.
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llvm-svn: 142691
2011-10-21 22:21:10 +00:00
846bcff7c7
Assembly parsing for 4-register variant of VLD1.
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llvm-svn: 142682
2011-10-21 20:35:01 +00:00
c4360fe575
Assembly parsing for 3-register variant of VLD1.
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llvm-svn: 142675
2011-10-21 20:02:19 +00:00
2f2e3c4737
ARM VLD parsing and encoding.
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Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
79ebc51c45
Tidy up. Trailing whitespace.
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llvm-svn: 142591
2011-10-20 17:28:20 +00:00
34957911e7
Removed set, but unused variables.
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Patch by Joe Abbey <jabbey@arxan.com>.
llvm-svn: 142223
2011-10-17 18:48:30 +00:00
8b478360ef
Fix a non-firing assert. Change:
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assert("bad SymbolicOp.VariantKind");
To:
assert(0 && "bad SymbolicOp.VariantKind");
llvm-svn: 142000
2011-10-14 20:50:26 +00:00
a7ad9f3932
Fix undefined shift. Patch by Ahmed Charles.
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llvm-svn: 141914
2011-10-13 23:36:06 +00:00
44f76eafae
SETEND is not allowed in an IT block.
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llvm-svn: 141874
2011-10-13 17:58:39 +00:00
a098a891ab
ARM addrmode5 represents the 'U' bit of the encoding backwards.
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The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.
llvm-svn: 141819
2011-10-12 21:59:02 +00:00
54a20ed0f1
Thumb2 assembly parsing and encoding for LDC/STC.
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llvm-svn: 141811
2011-10-12 20:54:17 +00:00
8007320902
addrmode2 is gone from these, so no need for the reg0 operand.
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llvm-svn: 141794
2011-10-12 18:11:24 +00:00
6a5c150e9c
Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.
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llvm-svn: 141339
2011-10-06 23:33:11 +00:00
5dcda64338
Adding back support for printing operands symbolically to ARM's new disassembler
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using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
llvm-svn: 141129
2011-10-04 22:44:48 +00:00
efc761a1eb
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
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Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
llvm-svn: 140834
2011-09-30 00:50:06 +00:00
f01e2de5e6
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
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llvm-svn: 140560
2011-09-26 21:06:22 +00:00
987a878946
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
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llvm-svn: 140415
2011-09-23 21:07:25 +00:00
ffa8428acf
Revert r140412. This affects more instructions than intended.
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llvm-svn: 140413
2011-09-23 21:02:01 +00:00
7591d0c363
Thumb2 register-shifted-register loads cannot target the PC or the SP.
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llvm-svn: 140412
2011-09-23 21:00:32 +00:00
163be01d69
tMOVSr is not allowed in an IT block either.
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llvm-svn: 140104
2011-09-19 23:57:20 +00:00
61e4604dd8
CPS instructions are UNPREDICTABLE inside IT blocks.
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llvm-svn: 140102
2011-09-19 23:47:10 +00:00
f902d92fc9
Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle.
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llvm-svn: 140079
2011-09-19 22:34:23 +00:00
05541f45f3
Thumb2 assembly parsing and encoding for TBB/TBH.
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llvm-svn: 140078
2011-09-19 22:21:13 +00:00
ddfcec92d9
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
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llvm-svn: 140032
2011-09-19 18:07:10 +00:00
502cd9d87a
Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB.
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llvm-svn: 139972
2011-09-16 23:30:01 +00:00
b925e935d7
Fix bitfield decoding based on Eli's feedback.
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llvm-svn: 139969
2011-09-16 23:04:48 +00:00
bcfa9a6f89
Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.
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llvm-svn: 139965
2011-09-16 22:42:36 +00:00
3ca958cd19
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
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llvm-svn: 139964
2011-09-16 22:29:48 +00:00
fe82365cb0
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
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llvm-svn: 139943
2011-09-16 21:08:33 +00:00
a0c3b97221
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
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llvm-svn: 139876
2011-09-15 23:38:46 +00:00
f1e384421a
Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.
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llvm-svn: 139736
2011-09-14 21:06:21 +00:00
a9ebf6fb64
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
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llvm-svn: 139522
2011-09-12 18:56:30 +00:00
53db43b560
LDM writeback is not allowed if Rn is in the target register list.
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llvm-svn: 139432
2011-09-09 23:13:33 +00:00
5bfb0e0a85
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
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llvm-svn: 139422
2011-09-09 22:24:36 +00:00
29cfe6c368
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
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llvm-svn: 139415
2011-09-09 21:48:23 +00:00
a05627ebaf
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
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llvm-svn: 139381
2011-09-09 18:37:27 +00:00
33d39536e6
All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.
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llvm-svn: 139329
2011-09-08 22:48:37 +00:00
2fefa427d5
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
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llvm-svn: 139328
2011-09-08 22:42:49 +00:00
7db8d697cf
Thumb2 assembly parsing and encoding for LDRD(immediate).
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Refactor operand handling for STRD as well. Tests for that forthcoming.
llvm-svn: 139322
2011-09-08 22:07:06 +00:00
f174959286
Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.
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llvm-svn: 139268
2011-09-08 00:11:18 +00:00
18d17aa6b7
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
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llvm-svn: 139256
2011-09-07 21:10:42 +00:00
8067df9503
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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llvm-svn: 139250
2011-09-07 19:42:28 +00:00
cd5612d3a5
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
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llvm-svn: 139240
2011-09-07 17:55:19 +00:00
Kevin Enderby