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1414 Commits

Author SHA1 Message Date
Venkatraman Govindaraju 6f0b450530 [Sparc]: Add memory operands for the frame references in the storeRegToStackSlot 
and loadRegFromStackSlot.

llvm-svn: 184935
 2013-06-26 12:40:16 +00:00
Chad Rosier 295bd43adb The getRegForInlineAsmConstraint function should only accept MVT value types. 
llvm-svn: 184642
 2013-06-22 18:37:38 +00:00
Bill Wendling a3cd350249 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 
llvm-svn: 184360
 2013-06-19 21:36:55 +00:00
David Blaikie b735b4d6db DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

llvm-svn: 184067
 2013-06-16 20:34:27 +00:00
Venkatraman Govindaraju 7dae9ce021 [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. 
llvm-svn: 183613
 2013-06-08 15:32:59 +00:00
Jakob Stoklund Olesen fdc9d0a991 Remember the anyext patterns. 
llvm-svn: 183589
 2013-06-07 22:59:29 +00:00
Jakob Stoklund Olesen 9f812b97ba Add missing zextloadi1 to i64 patterns. PR16721. 
llvm-svn: 183587
 2013-06-07 22:55:05 +00:00
Bill Wendling 6235c06ff8 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183565
 2013-06-07 20:35:25 +00:00
Roman Divacky 158d8069ad Fix a typo in asm string of BP* family of instructions. With this fix 
I am able to compile/assemble/link/run /bin/echo from FreeBSD.

llvm-svn: 183537
 2013-06-07 17:46:57 +00:00
Venkatraman Govindaraju dc82ac0dcc [Sparc]: Use cmp instruction instead of subcc to compare integers. 
llvm-svn: 183463
 2013-06-07 00:03:36 +00:00
Bill Wendling f77190855d Cache the TargetLowering info object as a pointer. 
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.

llvm-svn: 183361
 2013-06-06 00:43:09 +00:00
Venkatraman Govindaraju a54533ed78 Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 
llvm-svn: 183243
 2013-06-04 18:33:25 +00:00
Venkatraman Govindaraju f80d72f149 Sparc: Add support for indirect branch and blockaddress in Sparc backend. 
llvm-svn: 183094
 2013-06-03 05:58:33 +00:00
Venkatraman Govindaraju 774fe2e29a Sparc: When storing 0, use %g0 directly in the store instruction instead of 
using two instructions (sethi and store).

llvm-svn: 183090
 2013-06-03 00:21:54 +00:00
Venkatraman Govindaraju 0bbe1b210e Sparc: Combine add/or/sethi instruction with restore if possible. 
llvm-svn: 183088
 2013-06-02 21:48:17 +00:00
Venkatraman Govindaraju 3e8c7d98be Sparc: Perform leaf procedure optimization by default 
llvm-svn: 183083
 2013-06-02 02:24:27 +00:00
Venkatraman Govindaraju 28e2cd0e7e Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics as non-leaf functions. 
llvm-svn: 183079
 2013-06-01 20:42:48 +00:00
Venkatraman Govindaraju 3521dcdcc4 [Sparc] Generate correct code for leaf functions with stack objects 
llvm-svn: 183067
 2013-06-01 04:51:18 +00:00
Ahmed Bougacha b1a4d9da3b Make SubRegIndex size mandatory, following r183020. 
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.

llvm-svn: 183061
 2013-05-31 23:45:26 +00:00
Andrew Trick ad6d08ac6f Order CALLSEQ_START and CALLSEQ_END nodes. 
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.

Patch by Xiaoyi Guo!

This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.

llvm-svn: 182885
 2013-05-29 22:03:55 +00:00
NAKAMURA Takumi dbd3bbe126 SparcFrameLowering.cpp: Mark verifyLeafProcRegUse() as UNUSED. [-Wunused-function] 
llvm-svn: 182850
 2013-05-29 12:10:42 +00:00
Venkatraman Govindaraju ca0fe2f57e [Sparc] Add support for leaf functions in sparc backend. 
llvm-svn: 182822
 2013-05-29 04:46:31 +00:00
Andrew Trick ef9de2a739 Track IR ordering of SelectionDAG nodes 2/4. 
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

llvm-svn: 182703
 2013-05-25 02:42:55 +00:00
Jakob Stoklund Olesen f927800325 Also expand 64-bit bitcasts. 
llvm-svn: 182229
 2013-05-20 01:01:43 +00:00
Jakob Stoklund Olesen c7bc5fbc5c Implement spill and fill of I64Regs. 
llvm-svn: 182228
 2013-05-20 00:53:25 +00:00
Jakob Stoklund Olesen 751e9b8407 Mark i64 SETCC as expand so it is turned into a SELECT_CC. 
llvm-svn: 182227
 2013-05-20 00:28:36 +00:00
Jakob Stoklund Olesen 86c5469d26 Don't use %g0 to materialize 0 directly. 
The wired physreg doesn't work on tied operands like on MOVXCC.

Add a README note to fix this later.

llvm-svn: 182225
 2013-05-19 21:47:13 +00:00
Jakob Stoklund Olesen 92ebf1153e Select i64 values with %icc conditions. 
llvm-svn: 182224
 2013-05-19 20:38:21 +00:00
Jakob Stoklund Olesen 7ca944b9db Add floating point selects on %xcc predicates. 
llvm-svn: 182222
 2013-05-19 20:33:11 +00:00
Jakob Stoklund Olesen 4a78c86a6a Implement SPselectfcc for i64 operands. 
Also clean up the arguments to all the MOVCC instructions so the
operands always are (true-val, false-val, cond-code).

llvm-svn: 182221
 2013-05-19 20:20:54 +00:00
Venkatraman Govindaraju 3320e5a921 [Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers. 
Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode.

llvm-svn: 182219
 2013-05-19 20:07:20 +00:00
Jakob Stoklund Olesen ead983cec9 Handle i64 FrameIndex nodes in SPARC v9 mode. 
llvm-svn: 182216
 2013-05-19 19:14:24 +00:00
Venkatraman Govindaraju 641b0b5a21 [Sparc] Implements hasReservedCallFrame and hasFP. 
This is to generate correct framesetup code when the function
 has variable sized allocas.

llvm-svn: 182108
 2013-05-17 15:14:34 +00:00
Venkatraman Govindaraju 54bf611c79 [Sparc] Prevent instructions that defines or uses %o7 to be in call's delay slot. 
llvm-svn: 182063
 2013-05-16 23:53:29 +00:00
Rafael Espindola 227144c23c Remove the MachineMove class. 
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.

I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.

llvm-svn: 181680
 2013-05-13 01:16:13 +00:00
Rafael Espindola 140a837acd Remove unused argument. 
llvm-svn: 181618
 2013-05-10 18:16:59 +00:00
Jakob Stoklund Olesen 84ebe25db7 Passing arguments to varags functions under the SPARC v9 ABI. 
Arguments after the fixed arguments never use the floating point
registers.

llvm-svn: 179987
 2013-04-21 21:36:49 +00:00
Jakob Stoklund Olesen 65d3287282 Fix the SETHIimm pattern for 64-bit code. 
Don't ignore the high 32 bits of the immediate.

llvm-svn: 179985
 2013-04-21 21:18:03 +00:00
Jakob Stoklund Olesen a41f91ea8e Compile varargs functions for SPARCv9. 
With a little help from the frontend, it looks like the standard va_*
intrinsics can do the job.

Also clean up an old bitcast hack in LowerVAARG that dealt with
unaligned double loads. Load SDNodes can specify an alignment now.

Still missing: Calling varargs functions with float arguments.

llvm-svn: 179961
 2013-04-20 22:49:16 +00:00
Tim Northover a2b533906a Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE. 
llvm-svn: 179939
 2013-04-20 12:32:17 +00:00
Jakob Stoklund Olesen 73d1739bc4 Add 64-bit multiply and divide instructions for SPARC v9. 
llvm-svn: 179582
 2013-04-16 02:57:02 +00:00
Jakob Stoklund Olesen eed1072ff8 Use i32 for all SPARC shift amounts, even in 64-bit mode. 
Test case by llvm-stress.

llvm-svn: 179477
 2013-04-14 05:48:50 +00:00
Jakob Stoklund Olesen c3c28f8599 Add support for the abs64 SPARC v9 code model. 
For when 16 TB just isn't enough.

llvm-svn: 179474
 2013-04-14 05:10:36 +00:00
Jakob Stoklund Olesen c8fc76b078 Add support for the SPARC v9 abs44 code model. 
This is the default model for non-PIC 64-bit code. It supports
text+data+bss linked anywhere in the low 16 TB of the address space.

llvm-svn: 179473
 2013-04-14 04:57:51 +00:00
Jakob Stoklund Olesen 2e64d7ab1d Use target flags for printing SPARC asm operands. 
64-bit code models need multiple relocations that can't be inferred from
the opcode like they can in 32-bit code.

llvm-svn: 179472
 2013-04-14 04:35:19 +00:00
Jakob Stoklund Olesen e0fc832b77 Also put target flags on SPARC constant pool references. 
Constant pool entries are accessed exactly the same way as global
variables.

llvm-svn: 179471
 2013-04-14 04:35:16 +00:00
Jakob Stoklund Olesen dc1ed57858 Fix patterns for 64-bit pointers. 
This fixes the pic32 code model for SPARC v9.

llvm-svn: 179469
 2013-04-14 01:53:23 +00:00
Jakob Stoklund Olesen 1fb08a8b08 Add target flags to SPARC address operands. 
SDNodes and MachineOperands get target flags representing the %hi() and
%lo() assembly annotations that eventually become relocations.

Also define flags to be used by the 64-bit code models.

llvm-svn: 179468
 2013-04-14 01:33:32 +00:00
Jakob Stoklund Olesen 15b3e90081 Define SPARC code models. 
Currently, only abs32 and pic32 are implemented. Add a test case for
abs32 with 64-bit code. 64-bit PIC code is currently broken.

llvm-svn: 179463
 2013-04-13 19:02:23 +00:00
Jakob Stoklund Olesen 6a0a3eb53e Use the correct types when matching ADDRri patterns from frame indexes. 
It doesn't seem like anybody is checking types this late in isel, so no
test case.

llvm-svn: 179462
 2013-04-13 19:02:16 +00:00