llvm-project

Commit Graph

Author	SHA1	Message	Date
Zi Xuan Wu (Zeson)	08db089124	[CSKY] Fix the testcase error due to the verifyInstructionPredicates - Test cases for arch only has 16-bit instruction such as ck801/ck802 need compile with -mattr=+btst16 - Fix the GPR copy instruction with MOV16 for 16-bit only arch.	2022-07-21 15:53:50 +08:00
Zi Xuan Wu	27c18558e6	[CSKY] Add missing codegen pattern for 16-bit instruction In generic cpu model, there are only low 16 registers and little 32-bit instruction. CK801 is the cpu family with least basic features like generic model. Add test run and check for generic cpu model in original test case to cover basic LLVM IR functionality.	2022-03-29 16:05:30 +08:00

Author

SHA1

Message

Date

Zi Xuan Wu (Zeson)

08db089124

[CSKY] Fix the testcase error due to the verifyInstructionPredicates

- Test cases for arch only has 16-bit instruction such as ck801/ck802 need
compile with -mattr=+btst16
- Fix the GPR copy instruction with MOV16 for 16-bit only arch.

2022-07-21 15:53:50 +08:00

Zi Xuan Wu

27c18558e6

[CSKY] Add missing codegen pattern for 16-bit instruction

In generic cpu model, there are only low 16 registers and little 32-bit instruction. CK801 is the cpu
family with least basic features like generic model.

Add test run and check for generic cpu model in original test case to cover basic LLVM IR functionality.

2022-03-29 16:05:30 +08:00

2 Commits