llvm-project

Commit Graph

Author	SHA1	Message	Date
Zi Xuan Wu	27c18558e6	[CSKY] Add missing codegen pattern for 16-bit instruction In generic cpu model, there are only low 16 registers and little 32-bit instruction. CK801 is the cpu family with least basic features like generic model. Add test run and check for generic cpu model in original test case to cover basic LLVM IR functionality.	2022-03-29 16:05:30 +08:00
Zi Xuan Wu	a556ec8861	[CSKY] Complete codegen of basic arithmetic and load/store operations Complete basic arithmetic operations such as add/sub/mul/div, and it also includes converions and some specific operations such as bswap.Add load/store patterns to generate different addressing mode instructions. Also enable some infra such as copy physical register and eliminate frame index.	2021-12-09 11:40:20 +08:00

Author

SHA1

Message

Date

Zi Xuan Wu

27c18558e6

[CSKY] Add missing codegen pattern for 16-bit instruction

In generic cpu model, there are only low 16 registers and little 32-bit instruction. CK801 is the cpu
family with least basic features like generic model.

Add test run and check for generic cpu model in original test case to cover basic LLVM IR functionality.

2022-03-29 16:05:30 +08:00

Zi Xuan Wu

a556ec8861

[CSKY] Complete codegen of basic arithmetic and load/store operations

Complete basic arithmetic operations such as add/sub/mul/div, and it also includes converions
and some specific operations such as bswap.Add load/store patterns to generate different addressing mode instructions.

Also enable some infra such as copy physical register and eliminate frame index.

2021-12-09 11:40:20 +08:00

2 Commits